CY62148E MoBL
®
4-Mbit (512K × 8) Static RAM
4-Mbit (512K × 8) Static RAM
Features
■
■
■
■
Very high speed: 45 ns
Voltage range: 4.5 V to 5.5 V
Pin compatible with CY62148B
Ultra low standby power
❐
Typical standby current: 1 µA
❐
Maximum standby current: 7 µA (Industrial)
Ultra low active power
❐
Typical active current: 2.0 mA at f = 1 MHz
Easy memory expansion with CE, and OE features
Automatic power-down when deselected
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
Available in Pb-free 32-pin thin small outline package (TSOP) II
and 32-pin small-outline integrated circuit (SOIC)
[1]
packages
■
advanced circuit design to provide ultra low standby current. This
is ideal for providing More Battery Life™ (MoBL
) in portable
applications. The device also has an automatic power-down
feature that significantly reduces power consumption when
addresses are not toggling. Placing the device into standby
mode reduces power consumption by more than 99% when
deselected (CE HIGH). The eight input and output pins (I/O
0
through I/O
7
) are placed in a high impedance state when the
device is deselected (CE HIGH), Outputs are disabled (OE
HIGH), or during an active Write operation (CE LOW and WE
LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the eight I/O pins (I/O
0
through I/O
7
)
is then written into the location specified on the address pins (A
0
through A
18
).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appear on the I/O pins.
The CY62148E device is suitable for interfacing with processors
that have TTL I/P levels. It is not suitable for processors that
require CMOS I/P levels. Please see
Electrical Characteristics
on page 4
for more details and suggested alternatives.
For a complete list of related documentation,
click here.
■
■
■
■
Functional Description
The CY62148E is a high performance CMOS static RAM
organized as 512K words by 8-bits. This device features
Logic Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
CE
WE
OE
INPUT BUFFER
ROW DECODER
I/O
IO0
0
I/O
IO1
1
SENSE AMPS
I/O
IO2
2
I/O
IO3
3
I/O
IO4
4
I/O
IO5
5
I/O
IO6
6
I/O
512K x 8
ARRAY
COLUMN DECODER
POWER
DOWN
IO7
7
A13
A14
A15
A16
Note
1. SOIC package is available only in 55 ns speed bin.
A17
A18
Cypress Semiconductor Corporation
Document Number: 38-05442 Rev. *P
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 1, 2016
CY62148E MoBL
®
Contents
Pin Configurations ........................................................... 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 10
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagrams .......................................................... 12
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 18
Worldwide Sales and Design Support ....................... 18
Products .................................................................... 18
PSoC®Solutions ....................................................... 18
Cypress Developer Community ................................. 18
Technical Support ..................................................... 18
Document Number: 38-05442 Rev. *P
Page 2 of 18
CY62148E MoBL
®
Pin Configurations
Figure 1. 32-pin SOIC/TSOP II pinout
Top View
A
17
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A
15
A
18
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
Product Portfolio
Power Dissipation
Product
Range
CY62148ELL
CY62148ELL
TSOP II
SOIC
Industrial
Industrial /
Automotive-A
V
CC
Range (V)
Min
4.5
4.5
Typ
[2]
5.0
5.0
Max
5.5
5.5
45
55
Speed
(ns)
Operating I
CC
(mA)
f = 1 MHz
Typ
[2]
2
2
Max
2.5
2.5
f = f
max
Typ
[2]
15
15
Max
20
20
Standby I
SB2
(µA)
Typ
[2]
1
1
Max
7
7
Note
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25 °C.
Document Number: 38-05442 Rev. *P
Page 3 of 18
CY62148E MoBL
®
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
Supply voltage
to ground potential ............. –0.5 V to 6.0 V (V
CCmax
+ 0.5 V)
DC voltage applied to outputs
in high Z state
[3, 4]
............. –0.5 V to 6.0 V (V
CCmax
+ 0.5 V)
DC input voltage
[3, 4]
......... –0.5 V to 6.0 V (V
CCmax
+ 0.5 V)
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(per MIL-STD-883, Method 3015) .......................... > 2001 V
Latch-up current .................................................... > 200 mA
Operating Range
Device
CY62148E
Range
Ambient
Temperature
V
CC
[5]
Industrial / –40 °C to +85 °C 4.5 V to 5.5 V
Automotive-A
Electrical Characteristics
Over the operating range
Parameter
V
OH[8]
V
OL
V
IH
V
IL
Description
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Test Conditions
V
CC
= 4.5 V, I
OH
= –1 mA
V
CC
= 5.5 V, I
OH
= –0.1 mA
I
OL
= 2.1 mA
V
CC
= 4.5 V to 5.5 V
V
CC
= 4.5 V to 5.5 V For TSOPII
package
For SOIC
package
I
IX
I
OZ
I
CC
I
SB2 [10]
Input leakage current
V
CC
operating supply
current
Automatic CE
power-down current –
CMOS inputs
GND < V
I
< V
CC
f = f
max
= 1/t
RC
f = 1 MHz
V
CC
= V
CC(max)
,
I
OUT
= 0 mA
CMOS levels
Output leakage current GND < V
O
< V
CC
, output disabled
45 ns
Min Typ
[7]
2.4
–
–
2.2
–0.5
–
–1
–1
–
–
–
–
–
–
–
–
–
–
–
15
2
1
Max
–
3.4
[8]
0.4
0.8
–
+1
+1
20
2.5
7
2.4
–
–
–
–0.5
–1
–1
–
–
–
55 ns
[6]
Min Typ
[7]
–
–
–
–
–
–
–
–
15
2
1
Max
–
3.4
[8]
0.4
V
CC
+ 0.5
–
0.6
[9]
+1
+1
20
2.5
7
µA
µA
µA
mA
Unit
V
V
V
V
V
V
CC
+ 0.5 2.2
CE > V
CC
– 0.2 V,
V
IN
> V
CC
– 0.2 V or V
IN
< 0.2 V,
f = 0, V
CC
= V
CC(max)
Notes
3. V
IL(min)
= –2.0 V for pulse durations less than 20 ns for I < 30 mA.
4. V
IH(max)
= V
CC
+ 0.75 V for pulse durations less than 20 ns.
5. Full device AC operation assumes a minimum of 100 µs ramp time from 0 to V
CC(min)
and 200 µs wait time after V
CC
stabilization.
6. SOIC package is available only in 55 ns speed bin.
7. Typical values are included for reference and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25 °C.
8. Please note that the maximum V
OH
limit for this device does not exceed minimum CMOS V
IH
of 3.5V. If you are interfacing this SRAM with 5 V legacy processors
that require a minimum V
IH
of 3.5 V, please refer to Application Note
AN6081
for technical details and options you may consider.
9. Under DC conditions the device meets a V
IL
of 0.8 V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.6 V. This
is applicable to SOIC package only.
10. Chip enable (CE) must be HIGH at CMOS level to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
Document Number: 38-05442 Rev. *P
Page 4 of 18
CY62148E MoBL
®
Capacitance
Parameter
[11]
C
IN
C
OUT
Description
Input capacitance
Output capacitance
Test Conditions
T
A
= 25 °C, f = 1 MHz, V
CC
= V
CC(Typ)
Max
10
10
Unit
pF
pF
Thermal Resistance
Parameter
[11]
JA
JC
Description
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
32-pin SOIC
Package
51.57
25.01
32-pin TSOP II Unit
Package
59.10
12.19
C/W
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
V
CC
OUTPUT
R1
3.0 V
30 pF
INCLUDING
JIG AND
SCOPE
R2
GND
Rise Time = 1 V/ns
10%
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to:
THEVENIN
EQUIVALENT
OUTPUT
R
TH
V
TH
Parameter
[11]
R1
R2
R
TH
V
TH
5.0 V
1800
990
639
1.77
Unit
V
Note
11. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05442 Rev. *P
Page 5 of 18
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