In most cases, the device configuration for optimal phase noise
performance is different from the device configuration for optimal
cycle to cycle or period jitter. CyberClocks Online Software
includes algorithms to optimize performance for either
parameter.
Document Number: 001-53148 Rev. *F
Page 4 of 12
CY2XF33
Absolute Maximum Conditions
Parameter
V
DD
V
IN[1]
T
S
T
J
ESD
HBM
JA[2]
Description
Supply voltage
Input voltage, DC
Temperature, storage
Temperature, junction
ESD protection (human body model)
–
Relative to V
SS
Non operating
–
JEDEC STD 22-A114-B
Condition
Min
–0.5
–0.5
–55
–40
2000
64
Max
4.4
V
DD
+ 0.5
135
135
–
Unit
V
V
C
C
V
C/W
Thermal resistance, junction to ambient 0 m/s airflow
Operating Conditions
Parameter
V
DD
T
PU
T
A
3.3 V supply voltage range
2.5 V supply voltage range
Power up time for V
DD
to reach minimum specified voltage (power ramp is
monotonic)
Ambient temperature (commercial)
Ambient temperature (industrial)
Description
Min
3.135
2.375
0.05
0
–40
Typ
3.3
2.5
–
–
–
Max
3.465
2.625
500
70
85
Unit
V
V
ms
C
C
DC Electrical Characteristics
Parameter
I
DD[3]
Description
Operating supply current
Condition
V
DD
= 3.465 V, CLK = 150 MHz, output
terminated
V
DD
= 2.625 V, CLK = 150 MHz, output
terminated
V
OD
V
OD
V
OS
V
OS
V
IH
V
IL
I
IH0
I
IH1
I
IL0
I
IL1
C
IN0[4]
C
IN1[4]
LVDS differential output voltage
Change in V
OD
between
complementary output states
LVDS offset output voltage
Change in V
OS
between
complementary output states
Input high voltage
Input low voltage
Input high current, FS0 pin
Input high current, FS1 pin
Input low current, FS0 pin
Input low current, FS1 pin
Input capacitance, FS0 pin
Input capacitance, FS1 pin
V
DD
= 3.3 V or 2.5 V, defined in
Figure 3
as terminated in
Figure 2
V
DD
= 3.3 V or 2.5 V, defined in
Figure 3
as terminated in
Figure 2
V
DD
= 3.3 V or 2.5 V, defined in
Figure 4
as terminated in
Figure 2
V
DD
= 3.3 V or 2.5 V, R
TERM
= 100
between CLK and CLK#
–
–
Input = V
DD
Input = V
DD
Input = V
SS
Input = V
SS
–
–
Min
–
–
247
–
1.125
–
0.7 ×
V
DD
–
–
–
–50
–20
–
–
Typ
–
–
–
–
–
–
–
–
–
–
–
–
15
4
Max
120
115
454
50
1.375
50
–
0.3 ×
V
DD
115
10
–
–
–
–
Unit
mA
mA
mV
mV
V
mV
V
V
A
A
A
A
pF
pF
Notes
1. The voltage on any input or I/O pin cannot exceed the power pin during power up.
2. Simulated. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers
are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
3. I
DD
includes ~4 mA of current that is dissipated externally in the output termination resistors.
4. Not 100% tested, guaranteed by design and characterization.
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