Sets the drive strength of the output drivers to be 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) or HSTL (LOW) compatible. Used in
conjunction with V
DDQ
to set the interface levels.
Power supply for the device core and inputs
Power supply for the device outputs. When utilizing 2.5V LVTTL outputs, V
DDQ
should be connected to V
DD
.
Power supply return for all power
G
GL
Qn
RxS
TxS
V
DD
V
DDQ
GND
I
I
O
I
I
LVTTL
(5)
LVTTL
(5)
Adjustable
(2)
3 Level
(3)
3 Level
(3)
PWR
PWR
PWR
NOTES:
1. Inputs are capable of translating the following interface standards. User can select between:
Single-ended 2.5V LVTTL levels
Single-ended 1.8V LVTTL levels
or
Differential 2.5V/1.8V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL levels
2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate V
DDQ
voltage.
3. 3 level inputs are static inputs and must be tied to V
DD
or GND or left floating. These inputs are not hot-insertable or over-voltage tolerant.
4. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt pulses or
be able to tolerate them in down stream circuitry.
5. Pins listed as LVTTL inputs will accept 2.5V signals when RxS = HIGH or 1.8V signals when RxS = LOW or MID.
REVISION A 11/3/15
3
2.5V SINGLE DATA RATE
1:5 CLOCK BUFFER
TERABUFFER™
5T905 DATA SHEET
INPUT/OUTPUT SELECTION
(1)
Input
2.5V LVTTL SE
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
HSTL DSE
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
HSTL DIF
2.5V LVTTL SE
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
HSTL DSE
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
HSTL DIF
Output
2.5V LVTTL
Input
2.5V LVTTL SE
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
HSTL DSE
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
HSTL DIF
2.5V LVTTL SE
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
HSTL DSE
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
HSTL DIF
Output
eHSTL
1.8V LVTTL
HSTL
NOTE:
1. The INPUT/OUTPUT SELECTION Table describes the total possible combinations of input and output interfaces. Single-Ended (SE) inputs in a single-ended mode require the
A/V
REF
pin to be connected to GND. Differential Single-Ended (DSE) is for single-ended operation in differential mode, requiring a V
REF
. Differential (DIF) inputs are used only in differential
mode.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
V
IHH
V
IMM
V
ILL
I
3
Parameter
Input HIGH Voltage Level
(1)
Input MID Voltage Level
(1)
Input LOW Voltage Level
(1)
3-Level Input DC Current (RxS, TxS)
Test Conditions
3-Level Inputs Only
3-Level Inputs Only
3-Level Inputs Only
V
IN
= V
DD
V
IN
= V
DD
/2
V
IN
= GND
Min.
V
DD
– 0.4
V
DD
/2 – 0.2
—
—
–50
–200
Max
—
V
DD
/2 + 0.2
0.4
200
+50
—
Unit
V
V
V
μA
HIGH Level
MID Level
LOW Level
NOTE:
1. These inputs are normally wired to V
DD
, GND, or left floating. Internal termination resistors bias unconnected unputs to V
DD
/2.
2.5V SINGLE DATA RATE
1:5 CLOCK BUFFER
TERABUFFER™
4
REVISION A 11/3/15
5T905 DATA SHEET
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR HSTL
(1)
Symbol
Parameter
Input Characteristics
I
IH
Input HIGH Current
(9)
I
IL
Input LOW Current
(9)
V
IK
Clamp Diode Voltage
V
IN
DC Input Voltage
V
DIF
DC Differential Voltage
(2,8)
V
CM
DC Common Mode Input Voltage
(3,8)
V
IH
DC Input HIGH
(4,5,8)
V
IL
DC Input LOW
(4,6,8)
V
REF
Single-Ended Reference Voltage
(4,8)
Output Characteristics
V
OH
Output HIGH Voltage
V
OL
Output LOW Voltage
Test Conditions
V
DD
= 2.6V
V
I
= V
DDQ
/GND
V
DD
= 2.6V
V
I
= GND/V
DDQ
V
DD
= 2.4V, I
IN
= -18mA
Min.
—
—
—
- 0.3
0.2
680
V
REF
+ 100
—
—
V
DDQ
- 0.4
V
DDQ
- 0.1
—
—
Typ.
(7)
—
—
- 0.7
Max
±5
±5
- 1.2
+3.6
—
900
—
V
REF
- 100
—
—
—
0.4
0.1
Unit
μA
V
V
V
mV
mV
mV
mV
V
V
V
V
750
750
I
OH
= -8mA
I
OH
= -100μA
I
OL
= 8mA
I
OL
= 100μA
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. V
DIF
specifies the minimum input differential voltage (V
TR
- V
CP
) required for switching where V
TR
is the "true" input level and V
CP
is the "complement" input level. Differential mode only.
The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new
state.
3. V
CM
specifies the maximum allowable range of (V
TR
+ V
CP
) /2. Differential mode only.
4. For single-ended operation, in differential mode,
A/V
REF
is tied to the DC voltage V
REF
.
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
7. Typical values are at V
DD
= 2.5V, V
DDQ
= 1.5V, +25°C ambient.
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be referenced.
9. For differential mode (RxS = LOW), A and
A/V
REF
must be at the opposite rail.
POWER SUPPLY CHARACTERISTICS FOR HSTL OUTPUTS
(1)
Symbol
I
DDQ
I
DDQQ
I
DDD
I
DDDQ
I
TOT
I
TOTQ
Parameter
Quiescent V
DD
Power Supply Current
Quiescent V
DDQ
Power Supply Current
Dynamic V
DD
Power Supply
Current per Output
Dynamic V
DDQ
Power Supply
Current per Output
Total Power V
DD
Supply Current
Total Power V
DDQ
Supply Current
Test Conditions
(2)
V
DDQ
= Max., Reference Clock = LOW
(3)
Outputs enabled, All outputs unloaded
V
DDQ
= Max., Reference Clock = LOW
(3)
Outputs enabled, All outputs unloaded
V
DD
= Max., V
DDQ
= Max., C
L
= 0pF
V
DD
= Max., V
DDQ
= Max., C
L
= 0pF
V
DDQ
= 1.5V, F
REFERENCE CLOCK
= 100MHz, C
L
= 15pF
V
DDQ
= 1.5V, F
REFERENCE CLOCK
= 250MHz, C
L
= 15pF
V
DDQ
= 1.5V, F
REFERENCE CLOCK
= 100MHz, C
L
= 15pF
V
DDQ
= 1.5V, F
REFERENCE CLOCK
= 250MHz, C
L
= 15pF
Typ.
20
0.1
10
15
20
25
15
30
Max
30
0.3
20
30
30
40
30
60
Unit
mA
mA
μA/MHz
μA/MHz
mA
mA
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
stm32/stm8
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