NB4N507A
3.3V/5V, 50 MHz to 200 MHz
PECL Clock Synthesizer
Description
The NB4N507A is a precision clock synthesizer which generates a
very low jitter differential PECL output clock. It produces a clock
output based on an integer multiple of an input reference frequency.
The NB4N507A accepts a standard fundamental mode crystal,
using Phase-Locked-Loop (PLL) techniques, will produce output
clocks up to 200 MHz. In addition, the PLL circuitry will produce a
50% duty cycle square-wave clock output (see Figure 7).
The NB4N507A can be programmed to generate a selection of input
reference frequency multiples. An exact 155.52 MHz output clock can
be generated from a 19.44 MHz crystal and the x8 multiplier selection.
The NB4N507A is intended for low output jitter clock generation.
The PECL outputs are 15 mA open collector and must be DC loaded
and AC terminated. See Figures 4 and 6.
Features
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SOIC-16
D SUFFIX
CASE 751B
•
•
•
•
•
•
•
•
•
Input Crystal Frequency of 10 - 27 MHz
Enable Usage of Common Low-Cost Crystal
Differential PECL Output Clock Frequencies up to 200 MHz
Duty Cycle of 48%/52%
Operating Range: V
CC
= 3.0 V to 5.5 V
Ideal for SONET Applications and Oscillator Manufacturers
Available in Die Form
Packaged in 16-Pin Narrow SOIC
Pb-Free Packages are Available*
MARKING DIAGRAM
NB4N507AG
AWLYWW
Osc
PD
CP
VCO
Mult
PECL
CLKOUT
CLKOUT
OE
A
WL
Y
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
S0 S1
Figure 1. Simplified Logic Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2007
1
September, 2007 - Rev. 3
Publication Order Number:
NB4N507A/D
NB4N507A
V
DD
X1/CLK
Crystal
X2
Feedback
Multiplier
Select
S0 S1
GND
Oscillator
Buffer
Phase
Detector
Charge
Pump
PECL
Output
CLKOUT
VCO
CLKOUT
OE
Figure 2. NB4N507A Logic Diagram
Table 1. CLOCK MULTIPLIER SELECT TABLE
X1/CLK
V
DD
V
DD
S1
GND
GND
NC
CLKOUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X2
NC
S0
OE
NC
NC
NC
CLKOUT
S1
L
L
L
M
M
M
H
H
H
S0
L
M
H
L
M
H
L
M
H
Multiplier
9.72X*
10X
12X
6.25X
8X
5X
NA
3X
4X
*Example Crystal = 16 MHz, f
CLKOUT
= 155.52 MHz
L = GND
H = V
DD
M = OPEN
Figure 3. 16-Pin SOIC
(Top View)
Table 2. OE, OUTPUT ENABLE FUNCTION
OE
0
1
Function
Disable
Enable
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NB4N507A
Table 3. PIN DESCRIPTION
Pin #
SOIC-16
1
2,3
4
5,6
7,10,11,12,
15
8
9
13
Name
X1/CLK
V
DD
S1
GND
NC
CLKOUT
CLKOUT
OE
I/O
Crystal Input
Power Supply
Tri-Level Input
Power Supply
No Connect
PECL Output*
PECL Output*
(LV)CMOS/(LV)TTL
Input
Tri-Level Input
Crystal Input
Crystal or Clock Input
Positive Supply Voltage (3.0 V to 5.5 V)
Multiplier Select Pin; When Left Open, Defaults to V
DD
B
2
Negative Supply Voltage
Pin 10 does not require an external resistor. The NB4N507A will function with or
without a resistor on Pin 10.
Non-inverted differential PECL clock output.
Inverted differential PECL clock output.
Output Enable for the CLKOUT/CLKOUT Outputs. Outputs are
enabled when HIGH or when left open; OE pin has internal pullup resistor. Disables
both outputs when LOW. CLKOUT goes LOW, CLKOUT goes HIGH.
Multiplier Select Pin; When Left Open, Defaults to V
DD
B
2
Crystal Input
Description
14
16
S0
X2
*The PECL Outputs are 15 mA open collector and must be DC loaded and AC terminated. See Figures 4, 5 and 6.
Table 4. ATTRIBUTES
Characteristics
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Value
> 1 kV
> 150 V
> 1 kV
Level 1
UL 94 V-0 @ 0.125 in
1145 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Oxygen Index: 28 to 34
Table 5. MAXIMUM RATINGS
Symbol
V
CC
V
I
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply
Input Voltage
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction-to-Ambient)
Thermal Resistance (Junction-to-Case)
Wave Solder
Pb
Pb-Free
0 lfpm
500 lfpm
(Note 2)
< 3 sec @ 248°C
< 3 sec @ 260°C
SOIC-16
SOIC-16
Condition 1
GND = 0 V
Condition 2
Rating
6
GND - 0.5
≤
V
I
≤
V
DD
+ 0.5
-40 to +85
-65 to +150
100
60
33 to 36
265
265
Unit
V
V
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board - 2S2P (2 signal, 2 power).
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NB4N507A
Table 6. DC CHARACTERISTICS
(
V
DD
= 3.0 V to 5.5 V, GND = 0 V, T
A
= -40°C to +85°C (Note 3))
Symbol
I
DD
V
OH
V
OL
V
IH
V
IL
C
x
C
in
Characteristic
Power Supply Current
(does not include output load resistor current)
Output HIGH Voltage (Notes 5 & 6)
Output LOW Voltage (Notes 5 & 6)
Input HIGH Voltage (Note 4)
Input LOW Voltage,(Note 4)
Internal Crystal Capacitance, X1 & X2
Input Capacitance, S0, S1, OE
V
DD
= 5 V
V
DD
= 3.3 V
V
DD
= 5 V
V
DD
= 3.3 V
V
DD
= 5 V
V
DD
= 3.3 V
S0, S1, X1/CLK
OE
S0, S1, X1/CLK
OE
Min
15
10
3.95
2.57
3.12
1.90
V
DD
– 0.5
2.0
0
0
5.0
Typ
27
23
4.05
2.67
3.20
2.00
Max
35
30
4.15
2.77
3.30
2.10
V
DD
0.5
0.8
Unit
mA
mA
V
V
V
V
pF
pF
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. PECL output parameters vary 1:1 with V
DD
.
4. S0 and S1 default to V
DD
B
2 when left open.
Table 7. AC CHARACTERISTICS
(V
DD
= 3.0 V to 5.5 V, GND = 0 V, T
A
= -40°C to +85°C (Note 5))
Symbol
f
Xtal
f
CLK
f
OUT
V
out pk-pk
DC
PLL
BW
t
jitter (pd)
t
jitter (pd)
tr/tf
Characteristic
Crystal Input Frequency (Note 7)
Input Clock Frequency (Note 8)
Output Frequency Range
Output Amplitude
Clock Output Duty Cycle (Note 8)
PLL Bandwidth (Note 8)
Period Jitter (RMS, 1s, 10,000 Cycles)
Period Jitter (Peak-to-Peak, 10,000 Cycles)
Output Rise and Fall Times (Note 8)
50
270
Min
10
5
50
550
48
10
10
$20
500
680
52
Typ
Max
27
52
200
Unit
MHz
MHz
MHz
mV
%
kHz
ps
ps
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. PECL outputs loaded with external resistors for proper operation (see Figures 4, 5 and 6).
6. V
OH
and V
OL
can be set by the external resistors, which can be modified.
7. The crystal should be fundamental mode, parallel resonant. Do not use third overtone. For exact tuning when using a crystal, capacitors
should be connected from pins X1 to ground and X2 to ground. The value of these capacitors is given by the following equation, where CL
is the specified crystal load capacitance: Crystal caps (pF) = (CL-5) x 2. So, for a crystal with 16 pF load capacitance, use two 22 pF caps,
including board trace capacitance (see Figure 7).
8. Guaranteed by design and characterization.
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NB4N507A
Q
Q
15 mA
Current Source
GND
Figure 4. Output Structure
V
DD
GND
270
W
z = 50
W
D
PECL
Driver
62
W
V
DD
62
W
z = 50
W
z = 50
W
270
W
GND
GND
GND
PECL
Receiver
D
V
DD
NB4N507
z = 50
W
Figure 5. Evaluation Test Load for the NB4N507A
V
DD
V
DD
50
W
NB4N507A
Z = 50
W
Receiver
A
50
W
V
DD
Z = 50
W
GND = 0 V
Figure 6. Alternate Termination for Output Driver and Device Evaluation
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