BF 1009
Silicon N-Channel MOSFET Tetrode
•
For low noise, high gain controlled
input stages up to 1GHz
•
Operating voltage 9 V
•
Integrated stabilized bias network
3
4
2
1
VPS05178
ESD: Electrostatic discharge
sensitive device, observe handling precaution!
Type
BF 1009
Marking Ordering Code Pin Configuration
JKs
Q62702-F1613 1 = S
2=D
Package
3 = G2 4 = G1 SOT-143
Maximum Ratings
Parameter
Drain-source voltage
Continuos drain current
Gate 1/gate 2 peak source current
Gate 1 (external biasing)
Total power dissipation,
T
S
≤
76 °C0
Storage temperature
Channel temperature
Symbol
Value
12
25
10
3
200
-55 ...+150
150
V
mW
°C
Unit
V
mA
V
DS
I
D
±
I
G1/2SM
+
V
G1SE
P
tot
T
stg
T
ch
Thermal Resistance
Channel - soldering point
R
thchs
≤370
K/W
Note:
It is not recommended to apply external DC-voltage on Gate 1 in active mode.
Semiconductor Group
Semiconductor Group
1
1
Sep-09-1998
1998-11-01
BF 1009
Electrical Characteristics
at
T
A
= 25°C, unless otherwise specified.
Symbol
Values
Parameter
min.
DC characteristics
Drain-source breakdown voltage
typ.
-
-
-
-
-
-
10
0.9
max.
-
12
16
60
50
500
-
-
Unit
V
(BR)DS
±
V
(BR)G1SS
±
V
(BR)G2SS
+I
G1SS
±
I
G2SS
16
8
9
-
-
-
8
-
V
I
D
= 300 µA, -V
G1S
= 4 V, -
V
G2S
= 4 V
Gate 1 source breakdown voltage
±
I
G1S
= 10 mA,
V
G2S
=
V
DS
= 0
Gate 2 source breakdown voltage
±
I
G2S
= 10 mA,
V
G1S
= 0 V,
V
DS
= 0 V
Gate 1 source current
µA
nA
µA
mA
V
V
G1S
= 6 V,
V
G2S
= 0 V
Gate 2 source leakage current
±
V
G2S
= 8 V,
V
G1S
= 0 V,
V
DS
= 0 V
Drain current
I
DSS
I
DSO
V
G2S(p)
V
DS
= 9 V,
V
G1S
= 0 ,
V
G2S
= 6 V
Operating current (selfbiased)
V
DS
= 9 V,
V
G2S
= 6 V
Gate 2-source pinch-off voltage
V
DS
= 9 V,
I
D
= 100 µA
AC characteristics
Forward transconductance (self biased)
g
fs
C
g1ss
C
dss
G
ps
F
800
∆
G
ps
-
-
-
-
-
40
24
2.1
0.9
22
1.4
50
-
2.5
-
-
-
-
mS
pF
V
DS
= 9 V,
V
G2S
= 6 V,
f
= 1 kHz
Gate 1-input capacitance (self biased)
V
DS
= 9 V,
V
G2S
= 6 ,
f
= 1 MHz
Output capacitance (self biased)
V
DS
= 9 V,
V
G2S
= 6 ,
f
= 100 MHz
Power gain (self biased)
dB
V
DS
= 9 V,
V
G2S
= 6 ,
f
= 800 MHz
Noise figure (self biased)
V
DS
= 9 V,
V
G2S
= 6 ,
f
= 800 MHz
Gain control range (self biased)
V
DS
= 9 V,
V
G2S
= 1 V,
f
= 800 MHz
Semiconductor Group
Semiconductor Group
2
2
Sep-09-1998
1998-11-01
BF 1009
Total power dissipation
P
tot
=
f
(T
S
)
Drain current
I
D
=
f
(V
G2S
)
300
11
mA
mW
9
8
P
tot
200
I
D
150
100
50
0
0
120
°C
7
6
5
4
3
2
1
20
40
60
80
100
150
0
0.0
1.0
2.0
3.0
4.0
V
6.0
T
S
V
G2S
Insertion power gain
|
S
21
|
2
=
f
(V
G2S
)
Forward transfer admittance
|
Y
21
| =
f
(V
G2S
)
26
mS
10
dB
22
-5
20
| S
21
|
2
-10
-15
-20
-25
-30
-35
-40
-45
6
-50
-55
-60
-65
0.0
1.0
2.0
3.0
4.0
V
|Y
21
|
18
16
14
12
10
8
4
2
6.0
0
0.0
1.0
2.0
3.0
4.0
V
6.0
V
G2S
V
G2S
Semiconductor Group
Semiconductor Group
3
3
Sep-09-1998
1998-11-01
BF 1009
Gate 1 input capacitance
C
g1ss
=
f
(V
g2s
)
f
= 200MHz
Output capacitance
C
dss
=
f
(V
G2
)
f
= 200MHz
3.2
pF
3.2
mA
2.4
2.4
C
g1ss
2.0
C
dss
V
2.0
1.6
1.6
1.2
1.2
0.8
0.8
0.4
0.4
0.0
0.0
1.0
2.0
3.0
4.0
6.0
0.0
0.0
1.0
2.0
3.0
4.0
V
6.0
V
G2S
V
G2S
Semiconductor Group
Semiconductor Group
4
4
Sep-09-1998
1998-11-01
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