74AHC574; 74AHCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
Rev. 02 — 24 January 2008
Product data sheet
1. General description
The 74AHC574; 74AHCT574 are high-speed Si-gate CMOS devices and are pin
compatible with Low Power Schottky TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
The 74AHC574; 74AHCT574 are octal D-type flip-flops featuring separate D-type inputs
for each flip-flop and 3-state outputs for bus oriented applications. A clock (CP) and an
output enable (OE) input are common to all flip-flops.
The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold
times requirements on the LOW-to-HIGH CP transition.
When OE is LOW the contents of the 8 flip-flops are available at the outputs. When OE is
HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does
not affect the state of the flip-flops.
The 74AHC574; 74AHCT574 is functionally identical to the 74AHC564; 74AHCT564, but
has non-inverting outputs. The 74AHC574; 74AHCT574 is functionally identical to
the 74AHC374; 74AHCT374, but has a different pinning.
2. Features
I
I
I
I
I
I
I
I
I
Balanced propagation delays
All inputs have a Schmitt-trigger action
3-state non-inverting outputs for bus orientated applications
8-bit positive, edge-triggered register
Independent register and 3-state buffer operation
Common 3-state output enable input
For 74AHC574 only: operates with CMOS input levels
For 74AHCT574 only: operates with TTL input levels
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
N
CDM JESD22-C101C exceeds 1000 V
I
Multiple package options
I
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
NXP Semiconductors
74AHC574; 74AHCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AHC574D
74AHCT574D
74AHC574PW
74AHCT574PW
74AHC574BQ
74AHCT574BQ
−40 °C
to +125
°C
DHVQFN20
−40 °C
to +125
°C
TSSOP20
−40 °C
to +125
°C
Name
SO20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
Version
SOT163-1
SOT360-1
Type number
plastic dual in-line compatible thermal enhanced
SOT764-1
very thin quad flat package; no leads; 20 terminals;
body 2.5
×
4.5
×
0.85 mm
4. Functional diagram
2
3
4
5
6
7
8
9
D0
D1
D2
D3
D4
D5
D6
D7
FF1
to
FF8
3-STATE
OUTPUTS
Q0 19
Q1 18
Q2 17
Q3 16
Q4 15
Q5 14
Q6 13
Q7 12
11 CP
1 OE
mna800
Fig 1.
Functional diagram
D0
D1
D2
D3
D4
D5
D6
D7
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
FF1
CP
FF2
FF3
FF4
FF5
FF6
FF7
FF8
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
001aah077
Fig 2.
Logic diagram
© NXP B.V. 2008. All rights reserved.
74AHC_AHCT574_2
Product data sheet
Rev. 02 — 24 January 2008
2 of 18
NXP Semiconductors
74AHC574; 74AHCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
11
1
11
2
3
4
5
6
7
8
9
CP
D0
D1
D2
D3
D4
D5
D6
D7
OE
1
mna798
C1
EN
2
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
19
18
17
16
15
14
13
12
8
9
3
4
5
6
7
1D
19
18
17
16
15
14
13
12
mna446
Fig 3.
Logic symbol
Fig 4.
IEC logic symbol
74AHC_AHCT574_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 24 January 2008
3 of 18
NXP Semiconductors
74AHC574; 74AHCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
5. Pinning information
5.1 Pinning
74AHC574
74AHCT574
terminal 1
index area
20 V
CC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
GND
(1)
GND 10
CP 11
13 Q6
12 Q7
OE
2
3
4
5
6
7
8
9
1
D0
D1
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 CP
001aah037
74AHC574
74AHCT574
D2
D3
D4
D5
D6
D7
GND 10
001aah666
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 5.
Pin configuration SO20, TSSOP20
Fig 6.
Pin configuration DHVQFN20
5.2 Pin description
Table 2.
Symbol
OE
D[0:7]
GND
CP
Q[0:7]
V
CC
Pin description
Pin
1
2, 3, 4, 5, 6, 7, 8, 9
10
11
20
Description
3-state output enable input (active LOW)
data input
ground (0 V)
clock input (LOW-to-HIGH, edge triggered)
supply voltage
19, 18, 17, 16, 15, 14, 13, 12 3-state flip-flop output
74AHC_AHCT574_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 24 January 2008
4 of 18
NXP Semiconductors
74AHC574; 74AHCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
6. Functional description
Table 3.
Function table
[1]
Input
OE
Load and read register
Load register and disable output
L
L
H
H
[1]
H = HIGH voltage level;
h = HIGH voltage level one setup time prior to the HIGH-to-LOW CP transition;
L = LOW voltage level;
l = LOW voltage level one setup time prior to the HIGH-to-LOW CP transition;
Z = high-impedance OFF-state;
↑
= LOW-to-HIGH clock transition.
Operating mode
CP
↑
↑
↑
↑
Dn
l
h
l
h
Internal
flip-flop
L
H
L
H
Output
Qn
L
H
Z
Z
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
SO20 package
TSSOP20 package
DHVQFN20 package
[1]
[2]
[3]
[4]
Conditions
Min
−0.5
−0.5
Max
+7.0
+7.0
-
±20
±25
75
-
+150
500
500
500
Unit
V
V
mA
mA
mA
mA
mA
°C
mW
mW
mW
V
I
<
−0.5
V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
−0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
−20
-
-
-
−75
−65
T
amb
=
−40 °C
to +125
°C
[2]
[3]
[4]
-
-
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
P
tot
derates linearly with 8 mW/K above 70
°C.
P
tot
derates linearly with 5.5 mW/K above 60
°C.
P
tot
derates linearly with 4.5 mW/K above 60
°C.
74AHC_AHCT574_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 24 January 2008
5 of 18
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