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BM6205FS-E2: 产品描述Motor / Motion / Ignition Controllers & Drivers 3-Phase 600V Fan Drvr PrestoMOS; 产品类别半导体电源管理; 文件大小1MB，共30页; 制造商ROHM(罗姆半导体); 官网地址https://www.rohm.com/

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BM6205FS-E2概述

Motor / Motion / Ignition Controllers & Drivers 3-Phase 600V Fan Drvr PrestoMOS

BM6205FS-E2规格参数

参数名称	属性值
Product Attribute	Attribute Value
制造商 Manufacturer	ROHM(罗姆半导体)
产品种类 Product Category	Motor / Motion / Ignition Controllers & Drivers
RoHS	Details
封装 / 箱体 Package / Case	SSOP-54
系列 Packaging	Cut Tape
系列 Packaging	Reel
NumOfPackaging	2
工厂包装数量 Factory Pack Quantity	1000

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For Air-Conditioner Fan Motor

3-Phase Brushless Fan Motor

Driver

BM6205FS

General Description

This motor driver IC adopts PrestoMOS™ as the output

transistor, and put in a small full molding package with

the 120° square wave commutation controller chip and

the high voltage gate driver chip. The protection circuits

for overcurrent, overheating, under voltage lock out and

the high voltage bootstrap diode with current regulation

are built-in. It provides optimum motor drive system and

downsizing the built-in PCB of the motor.

Features

600V

PrestoMOS™ built-in

Output

current 2.5A

Bootstrap

operation by floating high side driver

(including diode)

120°

square wave commutation logic

PWM

control

Rotational

direction switch

FG

signal output with pulse number switch (4 or 12)

VREG

output (5V/30mA)

Protection

circuits provided: CL, OCP, TSD, UVLO,

MLP and the external fault input

Fault

output (open drain)

Applications

Air

conditioners; air purifiers; water pumps;

dishwashers; washing machines

Key Specifications

Output

MOSFET Voltage:

600V

Driver

Output Current (DC):

±2.5A (Max)

Driver

Output Current (Pulse):

±4.0A (Max)

Output

MOSFET DC On Resistance:

1.7Ω (Typ)

Duty

Control Voltage Range:

2.1V to 5.4V

Operating

Case Temperature:

-20°C to +100°C

Junction

Temperature:

+150°C

Power

Dissipation:

3.00W

Package

SSOP-A54_36

W (Typ) x D (Typ) x H (Max)

22.0 mm x 14.1 mm x 2.4 mm

SSOP-A54_36

Typical Application Circuit

VDC

GND

VCC

VSP

C2~C4

C13

C11

VREG

R11

R13

DTR

C10

R12

R10

C14

C12

Figure 1. Application Circuit Example

Product

structure : Semiconductor IC

This

product is not designed protection against radioactive rays

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Datasheet

7. Output Duty Pulse Width Limiter

Pulse width duty is controlled during PWM switching in order to ensure the operation of internal power transistor. The

controller doesn’t output pulse of less than T

MIN

(0.8µs minimum), nor output a duty pulse of D

MAX

or more. Dead time is

forcibly provided to prevent internal power transistors to turn-on simultaneously in upper and lower side in gate driver

output (for example, UH and UL) of each arm. This will not overlap the minimum time T

(1.6µs minimum). Because of

this, the maximum duty of the synchronous switching mode is 84% (typical).

8. PWM Switching Arm Setting

The PWM switching arm can choose one from the synchronous switching or the upper switching. When PC is “L”, the

switching mode is the synchronous. And also when PC is “H”, the switching mode is the upper switching. However, when

the hall cycle is about 1.4-Hz or less, the switching mode keeps the synchronous even if PC is “H”. When the PWM

control is entering to the testing mode, the controller forces PC pin voltage to ground and synchronous switching mode.

Therefore, when PC pin pull-up to VREG pin, at least a resistor with a value 10k

Ω

or more. The VSP offset voltage

(Figure 32) is buffered to PCT pin, to connect an external resistor between PCT pin and ground. The internal bias current

is determined by PCT voltage and the resistor value - V

PCT

/ R

PCT

-, and mixed to PC pin. Because you can freely

determine the slope by the resistance ratio of PC pin and PCT pin, which allows you to adjust the voltage command

value to switch the synchronous switching or the upper switching. Please select the R

PCT

value from 50 kΩ to 200 kΩ in

the range on the basis of 100 kΩ, because the PCT pin current capability is a 100 µA or less.

Upper/Lower

Upper

SPMIN

VSP

PCT

= VSP-V

SPMIN

PCT

PCL

PCT

PC: H

PC: L

Upper SW

Upper/Lower S W

1/2 V

REG

VSP

Figure 4. PWM Switching Arm Setting

9. Current Limiter (CL) Circuit and Overcurrent Protection (OCP) Circuit

The current limiter circuit can be activated by connecting a low value resistor for current detection between the output

stage ground (PGND) and the controller ground (GND). When the SNS pin voltage reaches or surpasses the threshold

value (V

SNS

, 0.5V typical), the controller forces all the upper switching arm inputs low (UH, VH, WH = L, L, L), thus

initiating the current limiter operation. When the SNS pin voltage swings below the ground, it is recommended to insert a

resistor - 1.5 kΩ or more - between SNS pin and PGND pin to prevent malfunction. Since this limiter circuit is not a latch

type, it returns to normal operation - synchronizing with the carrier frequency - once the SNS pin voltage falls below the

threshold voltage. A filter is built into the overcurrent detection circuit to prevent malfunctions, and does not activate when

a short pulse of less than T

MASK

is present at the input.

When the SNS pin voltage reaches or surpasses the threshold value (V

OVER

, 0.9V typical) because of the power fault or

the short circuit except the ground fault, the gate driver outputs low to the gate of all output MOSFETs, thus initiating the

overcurrent protection operation. Since this protection circuit is also not a latch type, it returns to normal operation

synchronizing with the carrier frequency.

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Datasheet

10. Under Voltage Lock Out (UVLO) Circuit

To secure the lowest power supply voltage necessary to operate the controller and the driver, and to prevent under

voltage malfunctions, the UVLO circuits are independently built into the upper side floating driver, the lower side driver

and the controller. When the supply voltage falls to V

UVL

or below, the controller forces driver outputs low. When the

voltage rises to V

UVH

or above, the UVLO circuit ends the lockout operation and returns the chip only after 32 carrier

periods (1.6ms for the default 20kHz frequency) to normal operation. Even if the controller returns to normal operation,

the output begins from the following control input signal.

The voltage monitor circuit (4.0V nominal) is built-in for the VREG voltage. Therefore, the UVLO circuit does not release

operation when the VREG voltage rising is delayed behind the VCC voltage rising even if VCC voltage becomes V

UVH

more.

11. Thermal Shutdown (TSD) Circuit

The TSD circuit operates when the junction temperature of the controller exceeds the preset temperature (125°C

nominal). At this time, the controller forces all driver outputs low. Since thermal hysteresis is provided in the TSD circuit,

the chip returns to normal operation when the junction temperature falls below the preset temperature (100°C nominal).

The TSD circuit is designed only to shut the IC off to prevent thermal runaway. It is not designed to protect the IC or

guarantee its operation in the presence of extreme heat. Do not continue to use the IC after the TSD circuit is activated,

and do not use the IC in an environment where activation of the circuit is assumed.

Moreover, it is not possible to follow the output MOSFET junction temperature rising rapidly because it is a gate driver

chip that monitors the temperature and it is likely not to function effectively.

12. Motor Lock Protection (MLP) Circuit

When the controller detects the motor locking during fixed time of 4 seconds nominal when each edge of the hall signal

doesn't input either, the controller forces all driver outputs low under a fixed time 20 seconds nominal, and self-returns to

normal operation. This circuit is enabled if the voltage force to VSP is over the duty minimum voltage V

SPMIN

, and note

that the motor cannot start up when the controller doesn’t detect the motor rotation by the minimum duty control. Even if

the edge of the hall signal is inputted within range of the OFF state by this protection circuit, it is ignored. But if the VSP

is forced to ground level once, the protection can be canceled immediately.

13. Hall Signal Wrong Input Detection

Hall element abnormalities may cause incorrect inputs that vary from the normal logic. When all hall input signals go high

or low, the hall signal wrong input detection circuit forces all driver outputs low. And when the controller detects the

abnormal hall signals continuously for four times or more motor rotation, the controller forces all driver outputs low and

latches the state. It is released if the duty control voltage VSP is forced to ground level once.

14. Internal Voltage Regulator

The internal voltage regulator VREG is output for the bias of the hall

element and the phase control setting. However, when using the VREG

function, be aware of the I

OMAX

value. If a capacitor is connected to the

ground in order to stabilize output, a value of 1 µF or more should be used.

In this case, be sure to confirm that there is no oscillation in the output.

VCC

VREG

HUP

HUN

HVP

HVN

HWP

HWN

Controller IC

Figure 5. VREG Output Pin Application Example

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BM6205FS-E2

BM6205FS-E2在线购买

BM6205FS-E2概述

BM6205FS-E2规格参数

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