PSMN4R0-25YLC
N-channel 25 V 4.5 mΩ logic level MOSFET in LFPAK
Rev. 01 — 2 December 2010
Product data sheet
1. Product profile
1.1 General description
Logic level enhancement mode N-channel MOSFET in LFPAK package. This product is
designed and qualified for use in a wide range of industrial, communications and domestic
equipment.
1.2 Features and benefits
High reliability Power SO8 package,
qualified to 175°C
Low parasitic inductance and
resistance
Optimised for 4.5V Gate drive utilising
Superjunction technology
Ultra low QG, QGD & QOSS for high
system efficiencies at low and high
loads
1.3 Applications
DC-to-DC converters
Load switching
Power OR-ing
Server power supplies
Sync rectifier
1.4 Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
T
j
Quick reference data
Parameter
drain-source
voltage
drain current
total power
dissipation
junction
temperature
drain-source
on-state
resistance
V
GS
= 4.5 V; I
D
= 20 A;
T
j
= 25 °C; see
Figure 12
V
GS
= 10 V; I
D
= 20 A;
T
j
= 25 °C; see
Figure 12
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
V
GS
= 10 V; T
mb
= 25 °C;
see
Figure 1
T
mb
= 25 °C; see
Figure 2
Min
-
-
-
-55
Typ
-
-
-
-
Max Unit
25
84
61
175
V
A
W
°C
Static characteristics
R
DSon
-
-
4.5
3.5
5.8
4.5
mΩ
mΩ
NXP Semiconductors
PSMN4R0-25YLC
N-channel 25 V 4.5 mΩ logic level MOSFET in LFPAK
Quick reference data
…continued
Parameter
Conditions
Min
-
Typ
3.5
Max Unit
-
nC
Table 1.
Symbol
Q
GD
Dynamic characteristics
gate-drain charge V
GS
= 4.5 V; I
D
= 20 A;
V
DS
12 V; see
Figure 14;
see
Figure 15
total gate charge
V
GS
= 4.5 V; I
D
= 20 A;
V
DS
= 12 V; see
Figure 14;
see
Figure 15
Q
G(tot)
-
10.9 -
nC
2. Pinning information
Table 2.
Pin
1
2
3
4
mb
Pinning information
Symbol Description
S
S
S
G
D
source
source
source
gate
mounting base; connected to
drain
mbb076
Simplified outline
mb
Graphic symbol
D
G
S
1 2 3 4
SOT669 (LFPAK)
3. Ordering information
Table 3.
Ordering information
Package
Name
PSMN4R0-25YLC
LFPAK
Description
Version
plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669
Type number
PSMN4R0-25YLC
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 2 December 2010
2 of 15
NXP Semiconductors
PSMN4R0-25YLC
N-channel 25 V 4.5 mΩ logic level MOSFET in LFPAK
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
T
sld(M)
V
ESD
I
S
I
SM
E
DS(AL)S
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
peak soldering temperature
electrostatic discharge voltage
source current
peak source current
non-repetitive drain-source
avalanche energy
MM (JEDEC JESD22-A115)
T
mb
= 25 °C
pulsed; t
p
≤
10 µs; T
mb
= 25 °C
V
GS
= 10 V; T
j(init)
= 25 °C; I
D
= 84 A;
V
sup
≤
25 V; R
GS
= 50
Ω;
unclamped;
see
Figure 3
V
GS
= 10 V; T
mb
= 25 °C; see
Figure 1
V
GS
= 10 V; T
mb
= 100 °C; see
Figure 1
pulsed; t
p
≤
10 µs; T
mb
= 25 °C;
see
Figure 4
T
mb
= 25 °C; see
Figure 2
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
25 °C
≤
T
j
≤
175 °C; R
GS
= 20 kΩ
Min
-
-
-20
-
-
-
-
-55
-55
-
200
-
-
-
Max
25
25
20
84
60
336
61
175
175
260
-
55
336
17.4
Unit
V
V
V
A
A
A
W
°C
°C
°C
V
A
A
mJ
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode
Avalanche ruggedness
100
I
D
(A)
80
003a a f 505
120
P
der
(%)
80
03na19
60
40
40
20
0
0
50
100
150
200
T
mb
( C)
0
0
50
100
150
T
mb
(°C)
200
Fig 1.
Continuous drain current as function of
mounting base temperature
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
PSMN4R0-25YLC
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 2 December 2010
3 of 15
NXP Semiconductors
PSMN4R0-25YLC
N-channel 25 V 4.5 mΩ logic level MOSFET in LFPAK
10
3
I
AL
(A)
10
2
003a a f 519
(1)
10
(2)
1
10
-1
10
-3
10
-2
10
-1
1
t
AL
(ms )
10
Fig 3.
10
4
I
D
(A)
10
3
Single pulse avalanche rating; avalanche current as a function of avalanche time
003a a f 506
10
2
Limit R
DS on
= V
DS
/ I
D
t
p
=10
s
DC
100
s
10
1 ms
1
10 ms
100 ms
10
-1
10
-1
1
10
V
DS
(V)
10
2
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
PSMN4R0-25YLC
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 2 December 2010
4 of 15
NXP Semiconductors
PSMN4R0-25YLC
N-channel 25 V 4.5 mΩ logic level MOSFET in LFPAK
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
thermal resistance
from junction to
mounting base
Conditions
see
Figure 5
Min
-
Typ
1.4
Max
2.4
Unit
K/W
10
Z
th(j-mb)
(K/W)
1
= 0.5
0.2
0.1
10
-1
003a a f 507
0.05
0.02
s ingle s hot
P
=
t
p
T
t
p
T
t
10
-2
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
t
p
(s )
1
Fig 5.
Transient thermal impedance from junction to mounting base as a function of pulse duration
PSMN4R0-25YLC
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 2 December 2010
5 of 15
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