NCV7751
Twelve Low-Side Relay
Drivers
The NCV7751 is an automotive grade twelve channel low−side
driver providing drive capability up to 600 mA per channel. Output
control is via a SPI communication and offers convenient reporting of
faults for open load (or short to ground), over load, and over
temperature conditions. Additionally, all the drivers have integrated
output clamps for inductive loads.
The NCV7751 is available in a SSOP−24 exposed pad package for
optimal thermal performance.
Features
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•
12 Channels
•
600 mA Low−Side Drivers
•
♦
SSOP24 NB EP
CASE 940AK
•
•
•
•
•
•
•
•
•
•
•
•
•
R
DS(on)
1.3
W
(typ), 2.5
W
(max)
Configurable SPI Control (16/24/32 Bit)
♦
Compatible with NCV7240
♦
Frame Error Detection
♦
Daisy Chain Capable
Power Up Without Open Circuit Detection Active (for LED
applications)
Low Quiescent Current in Sleep and Standby Modes
3.3 V and 5 V compatible Digital Input Supply Range
Fault Reporting
♦
Open Load Detection (Selectable)
♦
Over Load
♦
Over Temperature
Power−on Reset (VDD, VDDA)
SSOP−24 with an Exposed Pad
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These are Pb−Free Devices
Automotive Body Control Unit
Automotive Engine Control Unit
Relay Drive
LED Drive
Stepper Motor
MARKING DIAGRAM
NCV7751G
AWLYYWW
NCV7751 = Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
NCV7751DQR2G
Package
SSOP24−EP
(Pb−Free)
Shipping
†
2500 /
Tape & Reel
Applications
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2013
November, 2013
−
Rev. 0
1
Publication Order Number:
NCV7751/D
NCV7751
EN
VDDA
VDD
VDD
BIAS,
Supply Monitoring,
POR
Fault
Reporting
Register
Channel 1−12
OUT1
OUT2
Open Load
Fa u lt
OUT3
OUT4
OUT5
Over Load
Over Temperature
SI
OUT6
OUT7
OUT8
SCLK
CSB1
CSB2
Control
Logic
Low Side
Driver
OUT9
OUT10
OUT11
OUT12
SPI Input Logic Block
VDD
SO
GND GND GND GND
Figure 1. Block Diagram
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2
NCV7751
PACKAGE PIN DESCRIPTION
SSOP−24
EPAD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
EPAD
Symbol
GND
GND
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
GND
GND
VDD
CSB2
OUT9
OUT10
OUT11
OUT12
SO
SCLK
EN
SI
CSB1
VDDA
Exposed Pad
Ground.
Ground.
Channel 1 low−side drive output. Requires an external pull−up device for operation.
Channel 2 low−side drive output. Requires an external pull−up device for operation.
Channel 3 low−side drive output. Requires an external pull−up device for operation.
Channel 4 low−side drive output. Requires an external pull−up device for operation.
Channel 5 low−side drive output. Requires an external pull−up device for operation.
Channel 6 low−side drive output. Requires an external pull−up device for operation.
Channel 7 low−side drive output. Requires an external pull−up device for operation.
Channel 8 low−side drive output. Requires an external pull−up device for operation.
Ground.
Ground.
Digital Power Supply for SO output (3.3 V or 5 V).
Chip Select “Bar” Two (120 kW pull up resistor to VDD).
Channel 9 low−side drive output. Requires an external pull−up device for operation.
Channel 10 low−side drive output. Requires an external pull−up device for operation.
Channel 11 low−side drive output. Requires an external pull−up device for operation.
Channel 12 low−side drive output. Requires an external pull−up device for operation.
SPI serial data output. Output high voltage level referenced to pin VDD.
SPI clock (120 kW pull down resistor).
Global Enable (active high). (120 kW pull down resistor).
SPI serial data input (120 kW pull down resistor).
SPI Chip Select “Bar” One (120 kW pull up resistor to VDD).
Analog Power Supply Input voltage (5 V).
Connect to Ground or Leave Unconnected.
0.65 mm Pitch
Description
GND
GND
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDDA
CSB1
SI
EN
SCLK
SO
OUT12
OUT11
OUT10
OUT9
CSB2
VDD
Figure 2. NCV7751 Pinout
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3
NCV7751
MAXIMUM RATINGS
Symbol
Supply Input Voltage (VDDA, VDD)
DC
Digital I/O pin voltage
(EN, CSB1, CSB2 SCLK, SI)
(SO)
High Voltage Pins (OUTx)
DC
Peak Transient
Output Current (OUTx)
Clamping Energy
Maximum (single pulse)
Repetitive (multiple pulse)***
Operating Junction Temperature Range
Storage Temperature Range
ESD Capability, AEC−Q100−02
Human body model (100 pF, 1.5 kW) (OUTx pins)
Human body model (100 pF, 1.5 kW) (all other pins)
ESD Capability, AEC−Q100−03
Machine Model (200 pF)
AECQ10x−12
Short Circuit Reliability Characterization
PACKAGE
Moisture Sensitivity Level
Lead Temperature Soldering: SMD style only, Reflow (Note 1)
Pb−Free Part 60
−
150 sec above 217°C, 40 sec max at peak
Package Thermal Resistance (Note 2)
SSOP−24 EPAD
Junction−to−Ambient
R
qJA
57.9
MSL2
Treflow
2
265 peak
−
°C
°C/W
V
clpDcMax
V
clpAcMax
T
J
T
str
V
esd4k
V
esd2k
V
esd200
AECQ10x
Grade A
−
V
dcMax
V
ioMax
Min
−0.3
−0.3
−0.3
−0.3
−1
−
−
−40
−55
−4000
−2000
−200
Max
5.5
5.5
VDD + 0.3
36
44**
1.3
75
−
150
150
4000
2000
200
Unit
V
V
V
outxDcMax
V
outxAcMax
V
A
mJ
°C
°C
V
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
**Internally limited. Specification applies to unpowered and powered modes. (0 V to VDDA, 0 V to VDD)
***2M pulses (triangular), VS = 15 V, 63
W,
390 mH, T
A
= 25°C. (See Figure 3)
1. For additional information, see or download ON Semiconductor’s Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
and Application Note AND8083/D.
2. Values represent typical still air steady−state thermal performance on 2 oz. copper FR4 PCB with 645 mm
2
copper area.
Figure 3. Repetitive Clamping Energy Test
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4
NCV7751
unless otherwise specified).
Characteristic
GENERAL
Operating Current (VDDA)
ON Mode
(All Channels On)
Quiescent Current (VDDA)
Global Standby Mode
(All Channels Off)
Quiescent Current (VDDA)
Low Iq Mode
Operating Current (VDD)
ON Mode
(All Channels On)
Quiescent Current (VDD)
Global Standby Mode
(All Channels Off)
Quiescent Current (VDD)
Low Iq Mode
Total Quiescent Current
VDD + VDDA + OUT
x
SI = SCLK = 0 V, CSB1 = CSB2 = VDD
−40°C
≤
T
J
≤
125°C
T
J
= 150°C
SI = SCLK = EN = 0 V, CSB1 = CSB2 = VDD
−40°C
≤
T
J
≤
125°C
T
J
= 150°C
EN = high, SCLK = 0 V,
CSB1 = CSB2 = VDD = VDDA
CSB1 = CSB2 = VDD = VDDA, f
SCLK
= 0 Hz
−40°C
≤
T
J
≤
125°C
T
J
= 150°C
EN = 0 V
−40°C
≤
T
J
≤
125°C
T
J
= 150°C
T
J
= 125°C
OUT
x
= 18 V
EN = LHI = SCLK = SI = 0
VDDA = VDD = CSB1 = CSB2 = 5 V
VDDA rising
VDD = 3 V
IopVDDA
−
3
5
mA
ELECTRICAL CHARACTERISTICS
(3.0 V < VDD < VDDA, 4.5 V < VDDA (Note 3) < 5.5 V,
−40°C
v
T
J
v
150°C, EN = VDD
Conditions
Symbol
Min
Typ
Max
Unit
IstbyV
DDA
125
IstbyV
DDA
150
IqV
DDA
125
IqV
DDA
150
IopVDD
−
−
−
−
−
−
−
−
−
0.3
32
40
10
20
0.5
mA
mA
mA
IstbyV
DD
125
IstbyV
DD
150
IqV
DD
125
IqV
DD
150
Iq
tot
125
−
−
−
−
−
−
−
−
−
−
20
40
5
20
10
mA
mA
mA
Power−on Reset
threshold (VDDA)
Power−on Reset
Hysteresis (VDDA)
Power−on Reset
threshold (VDD)
Power−on Reset
Hysteresis (VDD)
Thermal Shutdown
(Note 4)
Thermal Hysteresis
OUTPUT DRIVER
Output Transistor R
DS(on)
Overload Detection
Current
Output Leakage
Output Clamp Voltage
V
DDApor
V
DDAhys
−
−
−
−
150
10
3.8
250
2.4
165
175
25
4.5
−
2.7
−
200
−
V
mV
V
mV
°C
°C
VDD rising
V
DDpor
V
DDAhys
Not ATE tested.
Not ATE tested.
T
sd
T
sHy
R
DS(on)LS
I
sd
IOUTx = 180 mA
−
0.6
−
−
36
1.3
0.95
−
−
40
2.5
1.3
1
5
44
W
A
mA
V
OUTx = 13.5 V, 25°C
OUTx = 13.5 V
VDD = 0 V to 5.5 V
VDDA = 0 V to 5.5 V
IOUTx = 180 mA
IOUTx =
−180
mA
I
snkLkg25
I
snkLkg
V
clmp
Output Body Diode Voltage
Open Load Detection
Threshold Voltage
Open Load Diagnostic
Sink Current
V
bdFwd
V
ol
−
1.0
20
−
1.75
60
1.5
2.5
100
V
V
mA
1 V < OUTx < 13.5 V, Output Disabled
I
ol
3. Reduced performance down to 4 V provided VDDA is not in Power−On Reset.
4. Each output driver is protected by its’ own individual thermal sensor.
5. Input signals H→L→H greater than 50usec are guaranteed to be detected.
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