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74LVC1G175GS132

产品描述Flip Flops 17ns 5.5V 250mW
产品类别半导体    逻辑   
文件大小788KB,共20页
制造商NXP(恩智浦)
官网地址https://www.nxp.com
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74LVC1G175GS132概述

Flip Flops 17ns 5.5V 250mW

74LVC1G175GS132规格参数

参数名称属性值
Product AttributeAttribute Value
制造商
Manufacturer
NXP(恩智浦)
产品种类
Product Category
Flip Flops
RoHSDetails
传播延迟时间
Propagation Delay Time
17 ns
电源电压-最小
Supply Voltage - Min
1.65 V
电源电压-最大
Supply Voltage - Max
5.5 V
最小工作温度
Minimum Operating Temperature
- 40 C
最大工作温度
Maximum Operating Temperature
+ 125 C
封装 / 箱体
Package / Case
XSON-6
系列
Packaging
Cut Tape
系列
Packaging
Reel
NumOfPackaging2
工厂包装数量
Factory Pack Quantity
5000

文档预览

下载PDF文档
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
Rev. 7 — 2 December 2016
Product data sheet
1. General description
The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type
flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q
output.
The master reset (MR) is an asynchronous active LOW input and operates independently
of the clock input. Information on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time
prior to the LOW-to-HIGH clock transition for predictable operation.
The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and
fall times.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant inputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V).
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V.
24
mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C.

 
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