Ordering number : EN8298B
LC87F5G32A
CMOS IC
FROM 32K byte, RAM 1024 byte on-chip
8-bit 1-chip Microcontroller
Overview
http://onsemi.com
The LC87F5G32A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle
time of 100ns, integrates on a single chip a number of hardware features such as 32K-byte flash ROM (onboard
programmable), 1024-byte RAM, an on-chip debugger, sophisticated 16-bit timers/counters (may be divided into 8-
bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with
a prescaler, a base timer serving as a time-of-day clock, a high-speed clock counter, a synchronous SIO interface
(with automatic block transmission/reception capabilities), an asynchronous/synchronous SIO interface, a UART
interface (full duplex), a 12-bit/8-bit 12-channel AD converter, two 12-bit PWM channels, a system clock frequency
divider, and a 22-source 10-vector interrupt feature.
Features
Flash
ROM
•
Capable of on-board-programming with wide range, 3.0 to 5.5V, of voltage source.
•
Block-erasable in 128 byte units
•
32768
×
8-bits (LC87F5G32A)
RAM
•
1024
×
9 bits (LC87F5G32A)
Minimum
Bus Cycle
•
100ns (10MHz)
Note : The bus cycle time here refers to the ROM read speed.
Minimum
Instruction Cycle Time
•
300ns (10MHz)
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
May, 2013
Ver.3.00
52307HKIM 20070123-S00009 No.8298-1/23
LC87F5G32A
Ports
•
Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1-bit units 30 (P1n,P2n,P30 to P36,P70 to P73,PWM0,PWM1,XT2)
Ports whose I/O direction can be designated in 4-bit units 8 (P0n)
•
Normal withstand voltage input port
1 (XT1)
•
Dedicated oscillator ports
2 (CF1, CF2)
•
Reset pins
1 (RES)
•
Power pins
6 (VSS1 to 3, VDD1 to 3)
Timers
•
Timer 0: 16-bit timer/counter with a capture register.
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register)
×
2-channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter
(with an 8-bit capture register)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3: 16-bit counter (with a 16-bit capture register)
•
Timer 1: 16-bit timer/counter that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + with an 8-bit prescaler 8-bit timer/counter
(with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler
×
2-channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from the lower-order 8-bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs)
(the lower-order 8-bits can be used as PWM.)
•
Timer 4: 8-bit timer with a 6-bit prescaler
•
Timer 5: 8-bit timer with a 6-bit prescaler
•
Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs)
•
Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs)
•
Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts programmable in 5 different time schemes
High-speed
Clock Counter
1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz).
2) Can generate output real-time.
SIO
•
SIO0: 8-bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle=4/3 tCYC)
3) Automatic continuous data transmission (1 to 256-bits, specifiable in 1 bit units, suspension and resumption
of data transmission possible in 1 byte units)
•
SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
UART
•
Full duplex
•
7/8/9 bit data bits selectable
•
1stop bit (2-bit in continuous data transmission)
•
Built-in baudrate generator
AD
Converter: 12-bits/8-bits
×
12-channels
•
12-bits/8-bits AD converter selectable
•
Automatic reference voltage generation controllable
No.8298-2/23
LC87F5G32A
PWM:
Multifrequency 12-bit PWM
×
2-channels
Remote
Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)
•
Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
Watchdog
Timer
•
External RC watchdog timer
•
Interrupt and reset signals selectable
Interrupts
•
22 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
1
2
3
4
5
6
7
8
9
10
Vector Address
00003H
0000BH
00013H
0001BH
00023H
0002BH
00033H
0003BH
00043H
0004BH
Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
INT0
INT1
INT2/T0L/INT4
INT3/INT5/base timer
T0H
T1L/T1H
SIO0/UART1 receive
SIO1/UART1 transmit
ADC/T6/T7
Port 0/T4/T5/PWM0, PWM1
Interrupt Source
• Priority Levels: X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
Subroutine
Stack Levels: 512 levels (the stack is allocated in RAM.)
High-speed
Multiplication/Division Instructions
•
16-bits
×
8-bits
(5 tCYC execution time)
•
24-bits
×
16-bits
(12 tCYC execution time)
•
16-bits ÷ 8-bits
(8 tCYC execution time)
•
24-bits ÷ 16-bits
(12 tCYC execution time)
Oscillation
Circuits
•
RC oscillation circuit (internal):
•
CF oscillation circuit:
•
Crystal oscillation circuit:
•
Frequency variable RC oscillation circuit (internal):
For system clock
For system clock, with internal Rf
For low-speed system clock, with internal Rf
For system clock
System
Clock Divider Function
•
Can run on low current.
•
The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, and 76.8μs
(at a main clock rate of 10MHz).
No.8298-3/23
LC87F5G32A
Standby
Function
•
HALT mode : Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) Canceled by a system reset or occurrence of an interrupt.
•
HOLD mode : Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, and crystal oscillators automatically stop operation.
2) There are three ways of resetting the HOLD mode.
(1) Setting the reset pin to the lower level.
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level.
(3) Having an interrupt source established at port 0.
•
X'tal HOLD mode : Suspends instruction execution and the operation of the peripheral circuits except the base timer.
1) The CF and RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are four ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level.
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level.
(3) Having an interrupt source established at port.
(4) Having an interrupt source established in the base timer circuit.
Onchip
Debugger
•
Supports software debugging with the IC mounted on the target board.
Package
Form
•
QIP48E(14×14): “Lead-free type”
•
SQFP48(7×7): “Lead-free type”
Development
Tools
•
Evaluation chip: LC87EV690
•
Emulator:
EVA62S + ECB876600D + SUB875G00 + POD48QFP
ICE-B877300 + SUB875G00 + POD48QFP
•
Onchip debugger: TCB87 TypeA + LC87F5G32A
TCB87 TypeB + LC87F5G32A
Flash
ROM Programming boards
Package
QIP48E(14×14)
SQFP48(7×7)
Programming boards
W87F55256Q
W87F55256SQ
Flash
ROM programmer
Maker
Single
Flash Support Group, Inc.
(Formerly Ando Electric Co., Ltd.)
Gang
AF9833 (Unit)
Our company
SKK (SANYO FWS)
After 01.84
After 1.02C (Install CD)
LC87F5G32A
Model
AF9708/AF9709/
AF9709B
AF9723 (Main body)
Supported version (Note)
After 02.40
After 02.04
LC87F5G32A FAST
Device
Note: Please check the latest version.
Same
package and pin assignment as mask ROM version.
1) LC875G00 series options can be set by using flash ROM data. Thus the board used for mass production can be
used for debugging and evaluation without modifications.
2) If the program for the mask ROM version is used, the usable ROM/RAM capacity is the same as the mask ROM
version.
No.8298-4/23
LC87F5G32A
Package Dimensions
unit : mm (typ)
3156A
17.2
0.8
14.0
36
37
25
24
7.0
9.0
Package Dimensions
unit : mm (typ)
3163B
9.0
7.0
36
37
25
24
14.0
17.2
48
13
1
0.5
12
0.18
0.15
48
1
1.0
(1.5)
0.35
12
13
(0.75)
0.15
1.7max
(1.5)
(2.7)
3.0max
0.1
SANYO : SQFP48(7X7)
0.1
SANYO : QIP48E(14X14)
Pin Assignment
P27/INT5/T1IN
P26/INT5/T1IN
P25/INT5/T1IN
P24/INT5/T1IN
P23/INT4/T1IN
P22/INT4/T1IN
P21/URX/INT4/T1IN
P20/UTX/INT4/T1IN
P07/T7O/AN7
P06/T6O/AN6
P05/CKO/AN5
P04/AN4
P36
P35
VDD3
VSS3
P34
P33
P32/DBGP2
P31/DBGP1
P30/DBGP0
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN
37
38
39
40
41
42
43
44
45
46
47
48
36
35
34
33
32
31
30
29
28
27
26
25
LC87F5G32A
24
23
22
21
20
19
18
17
16
15
14
13
P03/AN3
P02/AN2
P01/AN1
P00/AN0
VSS2
VDD2
PWM0
PWM1
P17/T1PWMH/BUZ
P16/T1PWML
P15/SCK1
P14/SI1/SB1
P73/INT3/T0IN
RES
XT1/AN10
XT2/AN11
VSS1
CF1
CF2
VDD1
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
1
2
3
4
5
6
7
8
9
10
11
12
Top view
QIP48E(14×14)
SQFP48(7×7)
"Lead-free Type"
"Lead-free Type"
No.8298-5/23
0.5
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