MGA-43828
925–960 MHz Linear Power Amplifier Module
Data Sheet
Description
The Avago MGA-43828 is a fully matched, highly linear
power amplifier (PA) designed for use in the 925-960
MHz band. Based on Avago’s proprietary 0.25
µm
GaAs
E-pHEMT technology, the device features high linearity,
gain and power-added efficiency (PAE) with integrated
power detector and shutdown functions. The MGA-43828
is ideal for use as a final stage PA for Small Cell base trans-
ceiver station (BTS) applications.
Features
•
High linearity performance : Max -50 dBc ACLR1
[1]
at 27
dBm linear output power (biased with 5.0 V supply)
•
High gain: 33 dB
•
Good efficiency
•
Fully matched
•
Built-in detector
•
GaAs E-pHEMT Technology
[2]
•
Low cost small package size: (5.0
×
5.0
×
0.9) mm
•
MSL3
•
Lead free/Halogen free/RoHS compliance
Component Image
(5.0
×
5.0
×
0.9) mm Package Outline
Specifications
A
VAGO
43828
YYWW
XXXX
TOP VIEW
Notes:
Package marking provides
orientation and identification
”43828” = Device part number
”YYWW” = Year and work week
”XXXX” = Assembly lot number
940 MHz; 5.0 V, Idqtotal =316 mA (typ), W-CDMA Test
model #1, 64DPCH downlink signal
•
•
•
•
PAE: 14.7%
27 dBm linear P
out
@ ACLR1 = -50 dBc
[1]
33 dB Gain
Detector range: 20 dB
Pin Configuration
24
Vdd3
22
Vdd3
23
Vdd3
26
Vdd2
25
Gnd
27
Gnd
28
NC
Applications
•
Final stage high linearity amplifier for Picocell and
Enterprise Femtocell PA targeted for small cell BTS
downlink applications.
21 Gnd
20 Gnd
19 RFout
18 RFout
17 RFout
16 Gnd
Notes:
1. W-CDMA Test model #1, 64DPCH downlink signal
2. Enhancement mode technology employs positive V
GS
, thereby
eliminating the need of negative gate voltage associated with
conventional depletion mode devices.
Gnd 1
Gnd 2
NC
NC
NC
3
5
7
RFin 4
Gnd 6
Functional Block Diagram
Vdd2
Vdd3
(5.0 x 5.0 x 0.9) mm
15 Gnd
VddBias
12
Vc3
10
Gnd
11
Gnd
13
Vdet
14
Vc2
9
NC
8
RFin
2
nd
Stage
3
rd
Stage
RFout
Biasing Circuit
Attention: Observe Precautions for
handling electrostatic sensitive devices.
Vc2 Vc3
VddBias
Vdet
ESD Machine Model = 60 V
ESD Human Body Model = 400 V
Refer to Avago Application Note A004R:
Electrostatic Discharge Damage and Control.
Absolute Maximum Rating
[1]
T
A
=25
°C
Symbol
V
dd
, V
ddBias
V
c
P
in,max
P
diss
T
j
T
STG
Thermal Resistance
[2,3]
Units
V
V
dBm
W
°C
°C
Parameter
Supply voltages, bias supply voltage
Control Voltage
CW RF Input Power
Total Power Dissipation
[3]
Junction Temperature
Storage Temperature
Absolute Max.
6.0
(V
dd
)
20
4.9
150
-65 to 150
q
jc
= 12
°C/W
Notes:
1. Operation of this device in excess of any of
these limits may cause permanent damage.
2. Thermal resistance measured using Infra-
Red Measurement Technique.
3. Board temperature (T
B
) is 25
°C
, for T
B
>91
°C
derate the device power at 83 mW per
°C
rise in Board (package belly) temperature.
Electrical Specifications
T
A
= 25
°C,
Vdd = VddBias = 5.0 V, Vc2=3.5 V, Vc3=2.8 V, Idqtotal = 316 mA, RF performance at 940 MHz, W-CDMA Test
model #1, 64DPCH downlink signal operation, unless otherwise stated.
Symbol
Vdd
Idqtotal
Gain
OP1dB
ACLR1 @ P
out
=27.0 dBm
PAE
|S11|
DetR
2fo
Parameter and Test Condition
Supply Voltage
Quiescent Supply Current
Gain
Output Power at 1dB Gain Compression
W-CDMA Test model #1, 64DPCH downlink signal
Power Added Efficiency
Input Return Loss, 50
Ω
source
Detector RF dynamic range
2fo Harmonics
(W-CDMA Test model #1, 64DPCH downlink signal)
Units
V
mA
dB
dBm
dBc
%
dB
dB
dBc
Min.
-
-
31
-
-
13
-
-
Typ.
5.0
316
33
36
-50
14.7
13.9
20
-35
Max.
-
560
-
-
-
-
-
-
2
Product Consistency Distribution Charts
[1]
LSL
LSL
35
34
33
31
32
36
Figure 1. Gain at P
out
=27 dBm, LSL= 31 dB, nominal = 33 dB
13
14
15
16
17
Figure 2. PAE at P
out
=27 dBm, LSL=13%, nominal = 14.7%
USL
200
250
300
350
400
450
500
550
600
600
650
700
750
800
850
900
Figure 3. Idqtotal, Nominal = 316 mA, USL=560 mA
Figure 4. Idd_Total at P
out
=27 dBm, nominal = 687 mA
-60 -58
-56
-54
-52
-50
-48
-46
-44
-42
Figure 5. ACLR1 at P
out
=27 dBm, nominal = -50.3 dBc
Note:
1. Distribution data sample size is 1500 samples taken from three wafer lots. T
A
= 25
°C,
Vdd=VddBias = 5.0 V, Vc2 = 3.5 V, Vc3 = 2.8 V, RF performance
at 940 MHz, unless otherwise stated. Future wafers allocated to this product may have nominal values anywhere between the upper and lower
limits.
3
MGA-43828 typical over-temperature performance at Vc2=3.5 V, Vc3=2.8 V (Vdd=VddBias=5 V) as shown in
Figure 27 and Vc2= 3.6 V, Vc3=2.5 V (Vdd=VddBias=5.5 V), unless otherwise stated.
40
85°C
35
S21
25°C
30
-40°C
25
20
15
10
5
S22
0
-5
-10
S11
-15
-20
-25
-30
-35
-40
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2
Frequency/GHz
40
35
85°C
S21
30
25°C
25
-40°C
20
15
10
5
S22
0
-5
-10
S11
-15
-20
-25
-30
-35
-40
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2
Frequency/GHz
S21,S11,S22/dB
Figure 6. Small-signal performance Over-temperature Vdd=VddBias=5.0 V
operating voltage
Figure 7. Small-signal performance Over-temperature Vdd=VddBias=5.5 V
operating voltage
S21,S11,S22/dB
-35
-40
-45
ACLR1/dBc
ACLR1_85°C
PAE_85°C
ACLR1_25°C
PAE_25°C
ACLR1_-40°C
PAE_-40°C
24
20
16
ACLR1/dBc
-35
-40
-45
PAE/%
ACLR1_85°C
PAE_85°C
ACLR1_25°C
PAE_25°C
ACLR1_-40°C
PAE_-40°C
24
20
16
12
8
4
19
20
21
22
23
24
25
26
27
28
29
30
0
PAE/%
-50
-55
-60
-65
19
20
21
22
23
24
25
Pout/dBm
26
27
28
29
12
8
4
30
0
-50
-55
-60
-65
Pout/dBm
Figure 8. Over-temperature ACLR1, PAE vs. P
out
@ 927.4 MHz
Vdd=VddBias=5.0 V operating voltage
Figure 9. Over-temperature ACLR1, PAE vs. P
out
@ 927.4 MHz
Vdd=VddBias=5.5 V operating voltage
4
MGA-43828 typical over-temperature performance at Vc2=3.5 V, Vc3=2.8 V (Vdd=VddBias=5 V) as shown in
Figure 27 and Vc2= 3.6 V, Vc3=2.5 V (Vdd=VddBias=5.5 V), unless otherwise stated.
-35
-40
-45
ACLR1/dBc
ACLR1_85°C
PAE_85°C
ACLR1_25°C
PAE_25°C
ACLR1_-40°C
PAE_-40°C
24
20
16
ACLR1/dBc
-35
-40
-45
PAE/%
-50
-55
-60
-65
19
20
21
22
23
24
25
P
out
/dBm
26
27
28
29
30
ACLR1_85°C
PAE_85°C
ACLR1_25°C
PAE_25°C
ACLR1_-40°C
PAE_-40°C
24
20
16
12
8
4
0
PAE/%
PAE/%
-50
-55
-60
-65
19
20
21
22
23
24
25
P
out
/dBm
26
27
28
29
30
12
8
4
0
Figure 10. Over-temperature ACLR1, PAE vs. P
out
@ 940 MHz
Vdd=VddBias=5.0V operating voltage
Figure 11. Over-temperature ACLR1, PAE vs. P
out
@ 940 MHz
Vdd=VddBias=5.5 V operating voltage
-35
-40
-45
ACLR1/dBc
ACLR1_85°C
PAE_85°C
ACLR1_25°C
PAE_25°C
ACLR1_-40°C
PAE_-40°C
24
20
16
12
8
4
19
20
21
22
23
25
P
out
/dBm
24
26
27
28
29
30
0
ACLR1/dBc
-35
-40
-45
-50
-55
-60
-65
19
20
21
22
23
24
25
P
out
/dBm
26
27
28
29
30
ACLR1_85°C
PAE_85°C
ACLR1_25°C
PAE_25°C
ACLR1_-40°C
PAE_-40°C
24
20
16
12
8
4
0
-50
-55
-60
-65
PAE/%
Figure 12. Over-temperature ACLR1, PAE vs. P
out
@ 957.6 MHz
Vdd=VddBias=5.0 V operating voltage
Figure 13. Over-temperature ACLR1, PAE vs. P
out
@ 957.6 MHz
Vdd=VddBias=5.5 V operating voltage
1200
1100
1000
900
I
dd
total/mA
Idd_Total_85°C
Idd_Total_25°C
Idd_Total_-40°C
1200
1100
1000
900
I
dd
total/mA
Idd_Total_85°C
Idd_Total_25°C
Idd_Total_-40°C
800
700
600
500
400
300
19
20
21
22
23
24
25
26
27
28
29
30
800
700
600
500
400
300
19
20
21
22
23
24
25
26
27
28
29
30
P
out
/dBm
P
out
/dBm
Figure 14. Over-temperature Idd_Total vs. P
out
@ 940 MHz
Vdd=VddBias=5.0 V operating voltage
Figure 15. Over-temperature Idd_Total vs. P
out
@ 940 MHz
Vdd=VddBias=5.5 V operating voltage
5
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