NCP3126
3 A Synchronous PWM
Switching Converter
The NCP3126 is a flexible synchronous PWM Switching Buck
Regulator. The NCP3126 is capable of producing output voltages as
low as 0.8 V. The NCP3126 also incorporates voltage mode control.
To reduce the number of external components, a number of features
are internally set including switching frequency. The NCP3126 is
currently available in an SOIC−8 package.
Features
8
1
SOIC−8 NB
D SUFFIX
CASE 751
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MARKING
DIAGRAM
8
3126
ALYWXG
G
•
•
•
•
•
•
•
•
•
•
•
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•
•
•
4.5 V to 13.2 V Operating Input Voltage Range
85 mW High−Side, 65 mW Low−Side Switches
Output Voltage Adjustable to 0.8 V
3 A Continuous Output Current
Fixed 350 kHz PWM Operation
1.0% Initial Output Accuracy
75% Max Duty Ratio
Over−Load Protection
Programmable Current Limit
This is a Pb−Free Device
Set Top Boxes
DVD Drives and HDD
LCD Monitors and TVs
Cable Modems
Telecom / Networking / Datacom Equipment
1
3126
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Typical Application
PIN CONNECTIONS
NCP3126
PGND
FB
COMP
AGND
(Top View)
1
VSW
ISET
VIN
BST
See detailed ordering and shipping information in the package
dimensions section on page 22 of this data sheet.
ORDERING INFORMATION
100
4.5 V
−
13.2 V
BST
3.3 V
EFFICIENCY (%)
95
90
85
80
75
70
65
0
0.5
1
1.5
2
OUTPUT CURRENT (A)
2.5
3
5V
VIN
VSW
PGND
NCP3126
ISET
COMP
FB1
AGND
Figure 1. Typical Application Circuit
Figure 2. Efficiency (V
IN
= 12 V) vs. Load Current
©
Semiconductor Components Industries, LLC, 2011
April, 2011
−
Rev. 2
1
Publication Order Number:
NCP3126/D
NCP3126
CIRCUIT DESCRIPTION
BST
+
−
−
+
10
mA
Fault
+
0.8 V
FB
−
−
S
Counter
DtoA
Clock
Ramp
OSC
VREG
OSC
+
−
Fault
0.7 V
Count
Latch
&
Logic
+
−
−
+
+
−
2V
VCC
VSW
+
PWM
Comp
R
PWM
OUT
Q
Fault
UVLO
POR
+
−
VOCTH
VIN
VREF
Latch
OLP
COMP
AGND
Figure 3. NCP3126 Block Diagram
ISET
PGND
Table 1. PIN DESCRIPTION
Pin
1
2
Pin Name
PGND
FB
Description
The PGND pin is the high current ground pin for the low−side MOSFET and the drivers. The pin should be
soldered to a large copper area to reduce thermal resistance.
Inverting input to the Operational Transconductance Amplifier (OTA). The FB pin in conjunction with the
external compensation, serves to stabilize and achieve the desired output voltage with voltage mode
control.
COMP pin is used to compensate the OTA which stabilizes the operation of the converter stage. Place
compensation components as close to the converter as possible.
The AGND pin serves as small−signal ground. All small−signal ground paths should connect to the AGND
pin at a single point, avoiding any high current ground returns.
Supply rail for the floating top gate driver. To form a boost circuit, use an external diode to bring the desired
input voltage to this pin (cathode connected to BST pin). Connect a capacitor (CBST) between this pin and
the VSW pin. Typical values for CBST range from 1 nF to 10 nF. Ensure that CBST is placed near the IC.
The VIN pin powers the internal control circuitry and is monitored by an undervoltage comparator. The VIN
pin is also connected to the internal power NMOSFET switches. The VIN pin has high dI/dt edges and must
be decoupled to PGND pin close to the pin of the device.
Current set pin and bottom gate MOSFET driver. Place a resistor to ground to set the current limit of the
converter.
The VSW pin is the connection of the drain and source of the internal N−MOSFETs. The VSW pin swings
from V
IN
when the high side switch is on to small negative voltages when the low side switch is on with high
dV/dt transitions.
3
4
5
COMP
AGND
BST
6
VIN
7
8
ISET
VSW
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2
NCP3126
Table 2. MAXIMUM RATINGS
Rating
Main Supply Voltage Input
Bootstrap Supply Voltage vs GND
Bootstrap Supply Voltage vs Ground (spikes
≤
50 ns)
Bootstrap Pin Voltage vs V
SW
High Side Switch Max DC Current
V
SW
Pin Voltage
Switching Node Voltage Excursion (200
mA)
Switch Pin voltage (spikes < 50 ns)
FB Pin Voltage
COMP/DISABLE
Low Side Driver Pin Voltage
Low Side Driver Pin Voltage (spikes
v
200 ns)
Rating
Thermal Resistance, Junction−to−Ambient
Thermal Resistance, Junction−to−Case
Storage Temperature Range
Junction Operating Temperature
Lead Temperature Soldering (10 sec):
Reflow (SMD styles only) Pb−Free
(Note 2)
(Note 3)
Symbol
V
IN
VBST
VBST spike
VBST−V
SW
IV
SW
V
SW
V
SWLIM
V
SWtr
VFB
VCOMP/DIS
VISET
VISET Spike
Symbol
R
qJA
R
qJC
T
stg
T
J
RF
Min
−0.3
−0.3
−5.0
−0.3
0
−0.3
−2.0
−5.0
−0.3
−0.3
−0.3
−2
Rating
110
183
170
−55
to 150
−40
to 125
260 peak
Max
15
15
35
15
3.0
30
35
40
5.5 < V
CC
5.5 < V
CC
15 < V
CC
15 < V
CC
Unit
V
V
V
V
A
V
V
V
V
V
V
V
Unit
°C/W
°C/W
°C
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The maximum package power dissipation limit must not be exceeded.
2. The value of
qJA
is measured with the device mounted on 1 in
2
FR−4 board with 1 oz. copper, in a still air environment with T
A
= 25°C. The
value in any given application depends on the user’s specific board design.
3. The value of
qJA
is measured with the device mounted on minimum footprint, in a still air environment with T
A
= 25°C. The value in any given
application depends on the user’s specific board design.
4. 60−180 seconds minimum above 237°C.
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3
NCP3126
Table 3. ELECTRICAL CHARACTERISTICS
(−40°C < T
J
< 125°C; V
IN
= 12 V, BST−VSW = 12 V, BST = 12 V, V
SW
= 24 V, for
Characteristic
Input Voltage Range
Boost Voltage Range
SUPPLY CURRENT
Quiescent Supply Current
Shutdown Supply Current
Boost Quiescent Current
UNDER VOLTAGE LOCKOUT
V
IN
UVLO Threshold
V
IN
UVLO Hysteresis
SWITCHING REGULATOR
VFB Feedback Voltage,
Control Loop in Regulation
Oscillator Frequency
Ramp−Amplitude Voltage
Minimum Duty Ratio
Maximum Duty Ratio
PWM COMPENSATION
Transconductance
Open Loop DC Gain
Output Source Current
Output Sink Current
Input Bias Current
ENABLE
Enable Threshold
SOFT−START
Delay to Soft−Start
SS Source Current
Switch Over Threshold
OVER−CURRENT PROTECTION
OCSET Current Source
OC Switch−Over Threshold
Fixed OC Threshold
PWM OUTPUT STAGE
High−Side Switch On−Resistance
Low−Side Switch On−Resistance
5. Guaranteed by design.
V
IN
= 12 V (Note 5)
V
IN
= 5 V (Note 5)
V
IN
= 12 V (Note 5)
V
IN
= 5 V (Note 5)
80
105
45
65
140
175
75
100
mW
mW
Sourced from ISET pin, before SS
−
−
−
10
700
375
−
−
mA
mV
mV
VFB < 0.8 V
VFB = 0.8 V
3
−
−
−
10.5
100
15
−
−
ms
mA
% of Vref
0.3
0.4
0.5
V
C
O
= 1 nF
V
FB
< 0.8 V
V
FB
> 0.8 V
3.0
55
60
60
−
−
70
125
125
0.160
5
−
200
200
1.0
ms
dB
mA
mA
T
J
= 0 to 25°C, 4.5 V < V
CC
< 13.2 V
−40°C
v
T
J
v
125°C, 4.5
v
V
CC
v
13.2 V
T
J
= 0 to 25°C, 4.5 V < V
CC
< 13.2 V
−40°C
v
T
J
v
125°C, 4.5
v
V
CC
v
13.2 V
792
784
300
290
0.8
−
70
800
800
350
350
1.1
5.5
75
808
816
400
410
1.4
−
80
mV
kHz
V
%
%
V
IN
Rising Edge
−
3.8
−
−
430
4.3
−
V
mV
VFB = 1.0 V, No Switching, V
IN
= 13.2 V
VFB = 1.0 V, COMP = 0 V, V
IN
= 13.2 V
VFB = 1.0 V, No Switching, V
IN
= 13.2 V
1.0
−
0.1
−
4.0
−
10.0
−
1.0
mA
mA
mA
Conditions
V
IN
−
GND
VBST
−
GND
Min
4.5
4.5
Typ
Max
13.2
26.5
Unit
V
V
min/max values unless otherwise noted.)
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NCP3126
TYPICAL CHARACTERISTICS
5.0
4.5
INPUT CURRENT (mA)
INPUT CURRENT (mA)
4.0
3.5
3.0
2.5
2.0
−60 −40 −20
V
CC
= 5 V
V
CC
= 12 V
25
23
21
19
17
15
13
11
0
20
40
60
80
100 120 140
9
0
V
CC
= 5 V
10
20
30
40
50
60
70
V
CC
= 12 V
T
J
, JUNCTION TEMPERATURE (°C)
T
J
, JUNCTION TEMPERATURE (°C)
Figure 4. I
CC
vs. Temperature
SOFT−START SOURCING CURRENT (mA)
14
13
V
ref
, REFERENCE (mV)
12
11
10
9
8
808
806
804
802
800
798
796
794
0
10
20
30
40
50
60
T
J
, JUNCTION TEMPERATURE (°C)
70
792
0
Figure 5. Input Current Switching vs.
Temperature
10
20
30
40
50
60
70
Figure 6. Soft−Start Sourcing Current vs.
Temperature
375
365
DUTY CYCLE (%)
355
345
335
325
6.0
5.0
4.0
3.0
2.0
1.0
0
T
J
, JUNCTION TEMPERATURE (°C)
Figure 7. Reference Voltage (V
ref
) vs.
Temperature
OLP THRESHOLD (mV)
V
CC
= 12 V
V
CC
= 5 V
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
T
J
, JUNCTION TEMPERATURE (°C)
T
J
, JUNCTION TEMPERATURE (°C)
Figure 8. OLP Threshold vs. Temperature
Figure 9. Minimum Active Duty Cycle vs.
Temperature
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