Supertex inc.
40MHz, 32-Channel Serial to Parallel Converter
with Push-Pull Outputs
Features
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HVCMOS
®
technology
5.0V logic and 12V supply rail
Output voltage up to +200V
Low power level shifting
Source/sink current minimum 50mA
40MHz equivalent data rate
Latched data outputs
Forward and reverse shifting options (DIR pin)
Chip select
Polarity function
HV7620
General Description
The HV7620 is a low-voltage serial to high-voltage parallel
converter with push-pull outputs. This device has been designed
for use as a driver for color AC plasma displays.
The device has 4 parallel 8-bit shift registers permitting data rates
four times the speed of one. The data is clocked in simultaneously
on all four data inputs with a single clock. Data is shifted in on a
low to high transition of the clock. The latches and control logic
perform the output enable function.
The DIR pin causes clockwise (CW) shifting of the data when
connected to VDD1, and counterclockwise (CCW) shifting when
connected to LVGND. Operation of the shift register is not affected
by the LE (latch enable) input. Transfer of data from the shift
registers to the latches occurs when the LE input is high. Data is
stored in the latches when LE is low. The current source on the
logic inputs provides active pull up when the input pins are open.
Functional Block Diagram
D
IN
A
D
OUT
A
CLK
8-Bit
Shift
Register
LE
QA1
BLA CS
POL
8
8-Bit
Latches
QA8
≈ ≈
BLB
≈
HV
OUT
A1
HV
OUT
B1
HV
OUT
C1
HV
OUT
D1
D
IN
B
D
OUT
B
8-Bit
Shift
Register
QB1
DIR
D
IN
C
D
OUT
C
8
8-Bit
Latches
QB8
≈ ≈
BLC
≈
8-Bit
Shift
Register
QC1
8
8-Bit
Latches
QC8
≈ ≈
BLD
≈
HV
OUT
A8
HV
OUT
B8
HV
OUT
C8
HV
OUT
D8
D
IN
D
D
OUT
D
8-Bit
Shift
Register
QD1
8-Bit
Latches
QD8
≈ ≈
8
Doc.# DSFP-HV7620
C112213
Supertex inc.
www.supertex.com
HV7620
Ordering Information / Availability
Part Number
HV7620PG-G
Package Option
64-Lead PQFP (3-sided)
Packing
66/tray
Pin Configuration
64
-G denotes a lead (Pb)-free / RoHS compliant package
Absolute Maximum Ratings
Parameter
Supply voltage, V
DD1
Supply voltage, V
DD2
Supply voltage, V
PP
Logic input levels
Continuous total power dissipation
1
Operating temperature range
Storage temperature range
Value
-0.5V to +14V
-0.5V to +14V
-0.5V to +225V
-2.0V to V
DD1
+ 2.0V
1200mW
-40°C to +85°C
-65°C to +150°C
1
64-Lead PQFP (3-sided)
(top view)
Product Marking
Top Marking
HV7 6 2 0P G
LLLLLLLLLL
YYWW
CCCC CCC C AA A
L = Lot Number
YY = Year Sealed
WW = Week Sealed
C = Country of Origin
A = Assembler ID
= “Green” Packaging
Package may or may not include the following marks: Si or
Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect
device reliability. All voltages are referenced to device ground.
Notes:
1. For operation above 25°C ambient derate linearly to maximum
operating temperature at 20mW/°C.
64-Lead PQFP (3-sided)
Typical Thermal Resistance
Package
64-Lead PQFP
θ
ja
41
O
C/W
Recommended Operating Conditions
Sym
V
DD1
V
DD2
V
PP
V
IH
V
IL
f
CLK
T
A
I
OD
I
GND(VPP)
V
PP(SLEW)
Parameter
Logic supply voltage
12V supply voltage
High voltage supply voltage
High-level input voltage
Low-level input voltage
Clock frequency
Operating temperature range
Allowable pulsed current through output diodes
1
Allowable pulsed V
PP
or HVGND current
1
Slew rate of V
PP
V
DD1
= 5.0V
V
DD1
= 12V
Min
4.5
10.8
50
V
DD1
-0.5V
0
-
-
-40
-
-
-
Max
V
DD2
13.2
200
V
DD1
0.5
10
5
+85
500
16
340
Units
V
V
V
V
V
MHz
MHz
°C
mA
A
V/µs
Notes:
1. The current pulse width = 500ns, duty cycle = 5%.
Doc.# DSFP-HV7620
C112213
2
Supertex inc.
www.supertex.com
HV7620
DC Electrical Characteristics
Sym
I
DD1
I
DD2
I
PP
I
DD1Q
I
DD2Q
V
OH
V
OL
I
IH
I
IL
V
GG
Parameter
V
DD1
supply current
V
DD2
supply current
High voltage supply current
Quiescent V
DD1
supply current
Quiescent V
DD2
supply current
High-level output
Low-level output
High-level logic input current
Low-level logic input current
HVGND to LVGND voltage difference
HV
OUT
Data OUT
HV
OUT
Data OUT
(Over operating supply voltages and temperature, unless otherwise noted, V
DD1
= 5.0V, V
DD2
= 12V, V
PP
= 200V and T
j
= 25°C)
Min
-
-
-
-
-
185
V
DD
-1
-
-
-
-
-1.0
Max
5.0
20
2.0
100
100
-
-
20
1.0
1.0
-10
1.0
Units
mA
mA
mA
µA
µA
V
V
µA
µA
V
Conditions
f
CLK
= 10MHz
V
DD2
= 13.2V, f
CLK
= 10MHz
All outputs high or low
All input = V
DD1
All input = V
DD1
I
O
= -50mA
I
O
= -100µA
I
O
= +50mA
I
O
= +100µA
V
IN
= V
DD1
V
IN
= 0V
---
AC Electrical Characteristics
Sym
f
CLK
t
WL
, t
WH
t
SU
t
H
t
ON
, t
OFF
t
WLE
t
DLE
t
SLE
t
DLF,
t
DLN
t
COF,
t
CON
t
DLH
t
DHL
Parameter
Clock frequency
Clock width high or low
(Logic signal inputs and data inputs have t
r
, t
f
≤
5ns. V
DD1
= 5.0V or 12V, V
DD2
= 12V, V
PP
= 200V and T
j
= 25°C)
Min
V
DD1
= 5.0V
V
DD1
= 12V
-
-
40
20
20
-
25
50
20
-
-
V
DD1
= 5.0V
V
DD1
= 12V
V
DD1
= 5.0V
V
DD1
= 12V
-
-
-
-
Max
10
5.0
-
-
-
275
-
-
-
250
275
250
100
250
100
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
Per register, C
L
= 15pF
---
---
---
C
L
= 15pF
---
---
---
---
---
C
L
= 15pF
C
L
= 15pF
Data set-up time before clock rises
Data hold time after clock rises
Time from latch enable to HV
OUT
LE pulse width
Delay time clock to LE low to high
LE set-up time before clock rises
BL or CS low to high to HV
OUT
Clock to HV
OUT
Delay time clock to data low
to high
Delay time clock to data high
to low
Doc.# DSFP-HV7620
C112213
3
Supertex inc.
www.supertex.com
HV7620
Input and Output Equivalent Circuits
VDD2
VDD1
VDD1
VPP
INPUT
DATA OUT
HV
OUT
LVGND
Logic Inputs
Logic Data Output
LVGND
HVGND
High Voltage Outputs
Switching Waveforms
V
IH
Data Input
CLK
50%
t
SU
50%
50%
Data Valid
t
H
50%
t
f
90%
50%
10%
t
r
10%
90%
50%
V
IL
V
IH
V
IL
V
OH
t
WL
t
DLH
Data Output
t
DHL
50%
t
WH
50%
V
OL
V
OH
50%
V
OL
50%
V
IH
V
IL
LE
t
DLE
t
COF
t
WLE
90%
t
SLE
V
OH
V
OL
V
OH
HV
OUT
t
OFF
HV
OUT
t
CON
BLA, BLB,
BLC, BLD, or CS
50%
10%
t
ON
V
OL
V
IH
V
IL
t
DLF
HV
OUT
t
DLN
90%
10%
V
OH
V
OL
Doc.# DSFP-HV7620
C112213
4
Supertex inc.
www.supertex.com
HV7620
Function Table
Inputs
Function
D
IN
A
X
X
X
X
X
H
X
X
D
IN
B
X
X
X
X
X
L
X
X
D
IN
C
X
X
X
X
X
L
X
X
D
IN
D
X
X
X
X
X
L
X
X
CLK
X
X
X
X
X
↑
X
↑
LE
X
X
X
X
X
H
L
H
DIR
X
X
X
X
X
X
X
H
BLA
X
X
L
H
H
H
H
H
BLB
X
X
X
H
H
H
H
H
BLC
X
X
X
H
H
H
H
H
BLD
X
X
X
H
H
H
H
H
CS
L
L
X
H
H
H
H
H
POL
L
H
H
H
L
H
H
X
A
N
→
A
N+1
A
N
→
A
N-1
H
A
H
L
L
HV
OUT
B
H
L
*
C
H
L
*
D
H
L
*
All O/P High
All O/P Low
“A”
†
Outputs
Low
Normal
Polarity
Outputs
Inverted
Transparent
Mode
Data Stored
Shift CW
A
No Inversion
Inversion
L
L
L
Stored data
B
N
→
B
N+1
B
N
→
B
N-1
C
N
→
C
N+1
C
N
→
C
N-1
D
N
→
D
N+1
D
N
→
D
N-1
Shift CCW
B
X
X
X
X
↑
H
L
H
H
H
H
H
X
Notes:
H = High level, L = Low level, X = Irrelevant,
↑
= Low to high transition.
* = Dependent on previous stage’s state before the last CLK
↑
for last LE high.
† = BLB, BLC and BLD will have similar effect on their respective output.
Power-up sequence:
1. GND (HV, LV)
2. V
DD1
3. V
DD2
4. V
PP
5. Logic Input Signals
To power down reverse the sequence above.
Doc.# DSFP-HV7620
C112213
5
Supertex inc.
www.supertex.com
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