74ACTQ00 Quiet Series™ Quad 2-Input NAND Gate
May 2007
74ACTQ00
Quiet Series™ Quad 2-Input NAND Gate
Features
■
I
CC
reduced by 50%
■
Guaranteed simultaneous switching noise level and
tm
General Description
The ACTQ00 contains four 2-input NAND gates and
utilizes Fairchild FACT Quiet Series™ technology to
guarantee quiet output switching and improve dynamic
threshold performance FACT Quiet Series features
GTO™ output control and undershoot corrector in
addition to a split ground bus for superior ACMOS
performance.
dynamic threshold performance
■
Improved latch-up immunity
■
Outputs source/sink 24mA
■
Has TTL-compatible inputs
Ordering Information
Order Number
74ACTQ00SC
74ACTQ00MTC
Package
Number
M14A
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram
Logic Symbol
IEEE/IEC
Pin Description
Pin Names
A
n
, B
n
O
n
Inputs
Outputs
Description
FACT™, FACT Quiet Series™, and GTO™ are trademarks of Fairchild Semiconductor Corporation.
©1990 Fairchild Semiconductor Corporation
74ACTQ00 Rev. 1.4
www.fairchildsemi.com
74ACTQ00 Quiet Series™ Quad 2-Input NAND Gate
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
I
IK
Supply Voltage
DC Input Diode Current
V
I
=
–0.5V
V
I
=
V
CC
+ 0.5V
V
I
I
OK
DC Input Voltage
DC Output Diode Current
V
O
=
–0.5V
V
O
=
V
CC
+ 0.5V
V
O
I
O
DC Output Voltage
Parameter
Rating
–0.5V to +7.0V
–20mA
+20mA
–0.5V to V
CC
+ 0.5V
–20mA
+20mA
–0.5V to V
CC
+ 0.5V
±50mA
±50mA
–65°C to +150°C
±300mA
140°C
DC Output Source or Sink Current
I
CC
or I
GND
DC V
CC
or Ground Current per Output Pin
T
STG
Storage Temperature
DC Latch-Up Source or Sink Current
T
J
Junction Temperature
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
I
V
O
T
A
∆
V /
∆
t
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Minimum Input Edge Rate:
Parameter
Rating
4.5V to 5.5V
0V to V
CC
0V to V
CC
–40°C to +85°C
125mV/ns
V
IN
from 0.8V to 2.0V, V
CC
@ 4.5V, 5.5V
©1990 Fairchild Semiconductor Corporation
74ACTQ00 Rev. 1.4
www.fairchildsemi.com
2
74ACTQ00 Quiet Series™ Quad 2-Input NAND Gate
FACT™ Noise Characteristics
The setup of a noise characteristics measurement is
critical to the accuracy and repeatability of the tests. The
following is a brief description of the setup used to
measure the noise characteristics of FACT.
V
OLP
/V
OLV
and V
OHP
/V
OHV
:
■
Determine the quiet output pin that demonstrates the
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50pF,
500Ω.
2. Deskew the HFS generator so that no two channels
have greater than 150ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the word generator channels
before testing. This will ensure that the outputs switch
simultaneously.
3. Terminate all inputs and outputs to ensure proper
loading of the outputs and that the input levels are at
the correct voltage.
4. Set the HFS generator to toggle all but one output at
a frequency of 1MHz. Greater frequencies will
increase DUT heating and effect the results of the
measurement.
5. Set the HFS generator input levels at 0V LOW and
3V HIGH for ACT devices and 0V LOW and 5V HIGH
for AC devices. Verify levels with an oscilloscope.
greatest noise levels. The worst case pin will usually
be the furthest from the ground pin. Monitor the output
voltages using a 50Ω coaxial cable plugged into a
standard SMB type connector on the test fixture. Do
not use an active FET probe.
■
Measure V
OLP
and V
OLV
on the quiet output during
the worst case transition for active and enable.
Measure V
OHP
and V
OHV
on the quiet output during
the worst case active and enable transition.
■
Verify that the GND reference recorded on the
oscilloscope has not drifted to ensure the accuracy
and repeatability of the measurements.
V
ILD
and V
IHD
:
■
Monitor one of the switching outputs using a 50Ω
coaxial cable plugged into a standard SMB type
connector on the test fixture. Do not use an active
FET probe.
■
First increase the input LOW voltage level, V
IL
, until
the output begins to oscillate or steps out a min of 2ns.
Oscillation is defined as noise on the output LOW
level that exceeds V
IL
limits, or on output HIGH levels
that exceed V
IH
limits. The input LOW voltage level at
which oscillation occurs is defined as V
ILD
.
■
Next decrease the input HIGH voltage level.V
IH
until
the output begins to oscillate or steps out a mine of
2ns. Oscillation is defined as noise on the output LOW
level that exceeds V
IL
limits, or on output HIGH levels
that exceed V
IH
limits. The input HIGH voltage level at
which oscillation occurs is defined as V
IHD
.
■
Verify that the GND reference recorded on the
oscilloscope has not drifted to ensure the accuracy
and repeatability of the measurements.
Notes:
7. V
OHV
and V
OLP
are measured with respect to ground
reference.
8. Input pulses have the following characteristics:
f
=
1MHz, t
r
=
3ns, t
f
=
3ns, skew
<
150ps.
Figure 1. Quiet Output Noise Voltage Waveforms
Figure 2. Simultaneous Switching Test Circuit
©1990 Fairchild Semiconductor Corporation
74ACTQ00 Rev. 1.4
www.fairchildsemi.com
5
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