19-3619; Rev 1; 3/07
KIT
ATION
EVALU
E
BL
AVAILA
14-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
MAX5890
General Description
The MAX5890 advanced 14-bit, 600Msps, digital-to-
analog converter (DAC) meets the demanding perfor-
mance requirements of signal synthesis applications
found in wireless base stations and other communica-
tions applications. Operating from 3.3V and 1.8V sup-
plies, the MAX5890 DAC supports update rates of
600Msps using high-speed LVDS inputs while consum-
ing only 297mW of power and offers exceptional
dynamic performance such as 80dBc spurious-free
dynamic range (SFDR) at f
OUT
= 30MHz.
The MAX5890 utilizes a current-steering architecture that
supports a 2mA to 20mA full-scale output current range,
and produces -2dBm to -22dBm full-scale output signal
levels with a double-terminated 50Ω load. The MAX5890
features an integrated 1.2V bandgap reference and con-
trol amplifier to ensure high-accuracy and low-noise per-
formance. A separate reference input (REFIO) allows for
the use of an external reference source for optimum flexi-
bility and improved gain accuracy.
The MAX5890 digital inputs accept LVDS voltage lev-
els, and the flexible clock input can be driven differen-
tially or single-ended, AC- or DC-coupled. The
MAX5890 is available in a 68-pin QFN package with an
exposed paddle (EP) and is specified for the extended
(-40°C to +85°C) temperature range.
Refer to the MAX5891 and MAX5889 data sheets for
pin-compatible 16-bit and 12-bit versions of the
MAX5890.
♦
600Msps Output Update Rate
♦
Low Noise Spectral Density: -162dBFS/Hz at
f
OUT
= 36MHz
♦
Excellent SFDR and IMD Performance
SFDR = 80dBc at f
OUT
= 30MHz (to Nyquist)
SFDR = 68dBc at f
OUT
= 130MHz (to Nyquist)
IMD = -95dBc at f
OUT
= 30MHz
IMD = -70dBc at f
OUT
= 130MHz
♦
ACLR = 73dB at f
OUT
= 122.88MHz
♦
2mA to 20mA Full-Scale Output Current
♦
LVDS-Compatible Digital Inputs
♦
On-Chip 1.2V Bandgap Reference
♦
Low 297mW Power Dissipation at 600Msps
♦
Compact (10mm x 10mm) QFN-EP Package
♦
Evaluation Kit Available (MAX5891EVKIT)
Features
Ordering Information
PART
MAX5890EGK-D
MAX5890EGK+D
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-
PACKAGE
68 QFN-EP*
68 QFN-EP*
PKG
CODE
G6800-4
G6800-4
Applications
Base Stations: Single/Multicarrier UMTS,
CDMA, GSM
Communications: Fixed Broadband Wireless
Access, Point-to-Point Microwave
Direct Digital Synthesis (DDS)
Cable Modem Termination Systems (CMTS)
Automated Test Equipment (ATE)
Instrumentation
*EP
= Exposed paddle.
D = Dry pack.
+Denotes
lead-free package.
Functional Diagram
MAX5890
OUTP
D0–D13
LVDS DATA
INPUTS
LVDS
RECEIVER
LATCH
600MHz
14-BIT DAC
OUTN
Selector Guide
PART
MAX5889
MAX5890
MAX5891
RESOLUTION
(BITS)
12
14
16
UPDATE RATE
LOGIC INPUT
(Msps)
600
600
600
LVDS
LVDS
LVDS
1.2V
REFERENCE
CLKP
CLKN
CLK
INTERFACE
POWER
DOWN
DACREF
REFIO
FSADJ
PD
Pin Configuration appears at end of data sheet.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
14-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
MAX5890
ABSOLUTE MAXIMUM RATINGS
AV
DD1.8
, DV
DD1.8
to AGND, DGND, DACREF,
and CGND.......................................................-0.3V to +2.16V
AV
DD3.3
, DV
DD3.3
, AV
CLK
to AGND, DGND,
DACREF, and CGND.........................................-0.3V to +3.9V
REFIO, FSADJ to AGND, DACREF,
DGND, and CGND ..........................-0.3V to (AV
DD3.3
+ 0.3V)
OUTP, OUTN to AGND, DGND, DACREF,
and CGND .......................................-1.2V to (AV
DD3.3
+ 0.3V)
CLKP, CLKN to AGND, DGND, DACREF,
and CGND..........................................-0.3V to (AV
CLK
+ 0.3V)
PD to AGND, DGND, DACREF,
and CGND.......................................-0.3V to (DV
DD3.3
+ 0.3V)
Digital Data Inputs (D0N–D13N, D0P–D13P) to AGND,
DGND, DACREF, and CGND ..........-0.3V to (DV
DD1.8
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C) (Note 1)
68-Pin QFN-EP (derate 28.6mW/°C above +70°C)....3333mW
Thermal Resistance
θ
JA
(Note 1) ....................................24°C/W
Operating Temperature Range ..........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range ............................-60°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
Note 1:
Thermal resistance based on a multilayer board with 4 x 4 via array in exposed-paddle area.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= 3.3V, AV
DD1.8
= DV
DD1.8
= 1.8V, external reference V
REFIO
= 1.2V, output load 50Ω double-terminat-
ed, transformer-coupled output, I
OUT
= 20mA, T
A
= -40°C to +85°C, unless otherwise noted. Specifications at T
A
≥
+25°C are guar-
anteed by production testing. Specifications at T
A
< +25°C are guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
STATIC PERFORMANCE
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Full-Scale Gain Error
Gain-Drift Tempco
Full-Scale Output Current
Output Compliance
Output Resistance
Output Capacitance
Output Leakage Current
DYNAMIC PERFORMANCE
Maximum DAC Update Rate
Minimum DAC Update Rate
f
CLK
= 500MHz,
-12dBFS, 20MHz
offset from the
carrier
f
OUT
= 36MHz
A
FULL-SCALE
= -3.5dBm
f
OUT
= 151MHz
A
FULL-SCALE
= -6.4dBm
600
1
-162
dBFS/Hz
-153
Msps
Msps
R
OUT
C
OUT
PD = high, power-down mode
I
OUT
Single-ended
INL
DNL
OS
GE
FS
External reference
Internal reference
External reference
2
-1.0
1
5
±1
Measured differentially
Measured differentially
-0.02
-4
14
±1
±0.5
±0.001
±1
±130
±100
20
+1.1
+0.02
+4
Bits
LSB
LSB
%FS
%FS
ppm/°C
mA
V
MΩ
pF
µA
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Noise Spectral Density
N
2
_______________________________________________________________________________________
14-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= 3.3V, AV
DD1.8
= DV
DD1.8
= 1.8V, external reference V
REFIO
= 1.2V, output load 50Ω double-terminat-
ed, transformer-coupled output, I
OUT
= 20mA, T
A
= -40°C to +85°C, unless otherwise noted. Specifications at T
A
≥
+25°C are guar-
anteed by production testing. Specifications at T
A
< +25°C are guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
f
CLK
= 200MHz,
0dBFS
Spurious-Free
Dynamic Range to
Nyquist
f
CLK
= 200MHz,
-12dBFS
SFDR
f
CLK
= 500MHz,
0dBFS
f
OUT
= 16MHz
f
OUT
= 30MHz
f
OUT
= 16MHz
f
OUT
= 30MHz
f
OUT
= 16MHz
f
OUT
= 30MHz
f
OUT
= 130MHz
f
OUT
= 200MHz
f
CLK
= 500MHz
Two-Tone IMD
TTIMD
f
CLK
= 500MHz
f
OUT1
= 29MHz,
f
OUT2
= 30MHz,
-6.5dBFS per tone
f
OUT1
= 129MHz,
f
OUT2
= 130MHz,
-6.5dBFS per tone
f
CLK
= 491.52MHz,
f
OUT
= 30.72MHz
f
CLK
= 491.52MHz,
f
OUT
= 122.88MHz
f
CLK
= 491.52MHz,
f
OUT
= 30.72MHz
f
CLK
= 491.52MHz,
f
OUT
= 122.88MHz
Output Bandwidth
REFERENCE
Internal Reference Voltage Range
Reference Input Voltage Range
Reference Input Resistance
Reference Voltage Temperature
Drift
Output Fall Time
Output Rise Time
Output Propagation Delay
V
REFIO
V
REFIOCR
R
REFIO
TCO
REF
Using external reference
1.14
0.10
1.2
1.2
10
±50
1.26
1.32
V
V
kΩ
ppm/°C
BW
-1dB
(Note 2)
76
MIN
TYP
89
85
79
78
81
80
71
55
-95
dBc
-70
dBc
MAX
UNITS
MAX5890
82
73
dB
74
67
1000
MHz
WCDMA single
carrier
Adjacent Channel
Leakage Power Ratio
ACLR
WCDMA four carriers
ANALOG OUTPUT TIMING (Figure 3)
t
FALL
t
RISE
t
PD
90% to 10% (Note 3)
10% to 90% (Note 3)
Reference to data latency (Note 3)
0.4
0.4
2.5
ns
ns
ns
_______________________________________________________________________________________
3
14-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
MAX5890
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= 3.3V, AV
DD1.8
= DV
DD1.8
= 1.8V, external reference V
REFIO
= 1.2V, output load 50Ω double-terminat-
ed, transformer-coupled output, I
OUT
= 20mA, T
A
= -40°C to +85°C, unless otherwise noted. Specifications at T
A
≥
+25°C are guar-
anteed by production testing. Specifications at T
A
< +25°C are guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
Output Settling Time
Glitch Impulse
Output Noise
TIMING CHARACTERISTICS
Input Data Rate
Data Latency
Data to Clock Setup Time
Data to Clock Hold Time
Clock Frequency
Minimum Clock Pulse-Width High
Minimum Clock Pulse-Width Low
Turn-On Time
CMOS LOGIC INPUT (PD)
Input Logic-High
Input Logic-Low
Input Current
Input Capacitance
LVDS INPUTS
Differential Input High
Differential Input Low
Internal Common-Mode Bias
Differential Input Resistance
Common-Mode Input Resistance
Input Capacitance
Clock Common-Mode Voltage
Minimum Differential Input
Voltage Swing
Minimum Common-Mode Voltage
Maximum Common-Mode
Voltage
V
IHLVDS
V
ILLVDS
V
ICMLVDS
R
IDLVDS
R
ICMLVDS
C
INLVDS
CLKP and CLKN are internally biased
(Notes 6, 7, 8)
(Notes 6, 7, 8)
+100
-1000
1.125
110
3.2
3
AV
CLK
/ 2
0.5
1
1.9
+1000
-100
1.375
mV
mV
V
Ω
kΩ
pF
V
V
P-P
V
V
V
IH
V
IL
I
IN
C
IN
-10
±1.8
3
0.7 x
DV
DD3.3
0.3 x
DV
DD3.3
+10
V
V
µA
pF
t
SETUP
t
HOLD
f
CLK
t
CH
t
CL
t
SHDN
Referenced to rising edge of clock (Note 4)
Referenced to rising edge of clock (Note 4)
CLKP, CLKN
CLKP, CLKN
CLKP, CLKN
External reference, PD falling edge to
output settle within 1%
0.6
0.6
350
-1.5
2.6
600
5.5
600
MWps
Clock
cycles
ns
ns
MHz
ns
ns
µs
N
OUT
SYMBOL
CONDITIONS
To 0.025% of the final value (Note 3)
Measured differentially
I
OUT
= 2mA
I
OUT
= 20mA
MIN
TYP
11
1
30
30
MAX
UNITS
ns
pV
•
s
pA/√Hz
DIFFERENTIAL CLOCK INPUTS (CLKP, CLKN)
4
_______________________________________________________________________________________
14-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= 3.3V, AV
DD1.8
= DV
DD1.8
= 1.8V, external reference V
REFIO
= 1.2V, output load 50Ω double-terminat-
ed, transformer-coupled output, I
OUT
= 20mA, T
A
= -40°C to +85°C, unless otherwise noted. Specifications at T
A
≥
+25°C are guar-
anteed by production testing. Specifications at T
A
< +25°C are guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
Input Resistance
Input Capacitance
POWER SUPPLIES
Analog Supply Voltage Range
Clock Supply Voltage Range
Digital Supply Voltage Range
AV
DD3.3
AV
DD1.8
AV
CLK
DV
DD3.3
DV
DD1.8
f
CLK
= 100MHz, f
OUT
= 16MHz
I
AVDD3.3
Analog Supply Current
I
AVDD1.8
f
CLK
= 500MHz, f
OUT
= 16MHz
f
CLK
= 600MHz, f
OUT
= 16MHz
f
CLK
= 100MHz, f
OUT
= 16MHz
f
CLK
= 500MHz, f
OUT
= 16MHz
f
CLK
= 600MHz, f
OUT
= 16MHz
f
CLK
= 100MHz, f
OUT
= 16MHz
Clock Supply Current
I
AVCLK
f
CLK
= 500MHz, f
OUT
= 16MHz
f
CLK
= 600MHz, f
OUT
= 16MHz
f
CLK
= 100MHz, f
OUT
= 16MHz
I
DVDD3.3
Digital Supply Current
I
DVDD1.8
f
CLK
= 500MHz, f
OUT
= 16MHz
f
CLK
= 600MHz, f
OUT
= 16MHz
f
CLK
= 100MHz, f
OUT
= 16MHz
f
CLK
= 500MHz, f
OUT
= 16MHz
f
CLK
= 600MHz, f
OUT
= 16MHz
f
CLK
= 100MHz, f
OUT
= 16MHz
f
CLK
= 500MHz, f
OUT
= 16MHz
Total Power Dissipation
P
DISS
f
CLK
= 600MHz, f
OUT
= 16MHz
Power-down, clock static low,
data input static
Power-Supply Rejection Ratio
PSRR
(Note 5)
3.135
1.710
3.135
3.135
1.710
3.3
1.8
3.3
3.3
1.8
26.5
26.5
26.5
11.3
50
60
2.8
2.8
2.8
0.2
0.2
0.2
10.6
43
50.5
137
264
297
13
±0.025
µW
%FS
298
mW
49
0.5
mA
3.6
mA
58
28.5
mA
3.465
1.890
3.465
3.465
1.890
V
V
V
SYMBOL
R
CLK
C
CLK
Single-ended
CONDITIONS
MIN
TYP
5
3
MAX
UNITS
kΩ
pF
MAX5890
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
This parameter does not include update-rate-dependent effects of sin(x)/x filtering inherent in the MAX5890.
Parameter measured single-ended with 50Ω double-terminated outputs.
Not production tested. Guaranteed by design.
Parameter defined as the change in midscale output caused by a
±5%
variation in the nominal supply voltages.
Not production tested. Guaranteed by design.
Differential input voltage defined as V
D_P
- V
D_N
.
V
D_N
V
IHLVDS
V
D_P
V
ILLVDS
Note 8:
Combination of logic-high/-low and common-mode voltages must not exceed absolute maximum rating for D_P/D_N inputs.
_______________________________________________________________________________________
5
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