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74CBTLV3125
4-bit bus switch
Rev. 4 — 9 November 2016
Product data sheet
1. General description
The 74CBTLV3125 provides a 4-bit high-speed bus switch with separate output enable
inputs (1OE to 4OE). The low on-state resistance of the switch allows connections to be
made with minimal propagation delay. The switch is disabled (high-impedance OFF-state)
when the output enable (nOE) input is HIGH.
To ensure the high-impedance OFF-state during power-up or power-down, nOE should be
tied to the V
CC
through a pull-up resistor. The minimum value of the resistor is determined
by the current-sinking capability of the driver.
Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 2.3 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features and benefits
Supply voltage range from 2.3 V to 3.6 V
Standard ’125’-type pinout
High noise immunity
Complies with JEDEC standard:
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM AEC-Q100-011 revision B exceeds 1000 V
5
switch connection between two ports
Rail to rail switching on data I/O ports
CMOS low power consumption
Latch-up performance exceeds 250 mA per JESD78B Class I level A
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74CBTLV3125
4-bit bus switch
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74CBTLV3125DS
74CBTLV3125PW
74CBTLV3125BQ
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
SSOP16
[1]
TSSOP14
Description
plastic shrink small outline package; 16 leads;
body width 3.9 mm; lead pitch 0.635 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT519-1
SOT402-1
SOT762-1
Type number
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5
3
0.85 mm
[1]
Also known as QSOP16.
4. Functional diagram
Fig 1.
Logic symbol
Fig 2.
Logic diagram (one switch)
74CBTLV3125
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 4 — 9 November 2016
2 of 18
NXP Semiconductors
74CBTLV3125
4-bit bus switch
5. Pinning information
5.1 Pinning
(1) The die substrate is attached to
this pad using conductive die
attach material. It can not be
used as a supply pin or input.
Fig 3.
Pin configuration
SOT519-1 (SSOP16)
Fig 4.
Pin configuration
SOT402-1 (TSSOP14)
Fig 5.
Pin configuration
SOT762-1 (DHVQFN14)
5.2 Pin description
Table 2.
Symbol
1OE, 2OE, 3OE, 4OE
1A, 2A, 3A, 4A,
1B, 2B, 3B, 4B
GND
V
CC
n.c.
Pin description
Pin
SOT519-1
2, 5, 12, 15
3, 6, 11, 14
4, 7, 10, 13
8
16
1, 9
SOT402-1 and SOT762-1
1, 4, 10, 13
2, 5, 9, 12
3, 6, 8, 11
7
14
-
output enable input
A input/output
B output/input
ground (0 V)
positive supply voltage
not connected
Description
6. Functional description
Table 3.
L
H
[1]
H = HIGH voltage level; L = LOW voltage level.
Function table
[1]
Function switch
ON-state
OFF-state
Output enable input OE
74CBTLV3125
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 4 — 9 November 2016
3 of 18
NXP Semiconductors
74CBTLV3125
4-bit bus switch
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
SW
I
IK
I
SK
I
SW
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input voltage
switch voltage
input clamping current
switch clamping current
switch current
supply current
ground current
storage temperature
total power dissipation
Conditions
control inputs
enable and disable mode
V
I
<
0.5
V
V
I
<
0.5
V
V
SW
= 0 V to V
CC
[1]
[2]
Min
0.5
0.5
0.5
50
50
-
-
100
65
Max
+4.6
+4.6
V
CC
+ 0.5
-
-
128
+100
-
+150
500
Unit
V
V
V
mA
mA
mA
mA
mA
C
mW
T
amb
=
40 C
to +125
C
[3]
-
The minimum input voltage rating may be exceeded if the input clamping current ratings are observed.
The switch voltage ratings may be exceeded if switch clamping current ratings are observed
For SSOP16 and TSSOP14 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
For DHVQFN14 packages: P
tot
derates linearly with 4.5 mW/K above 60
C.
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
SW
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
input voltage
switch voltage
ambient temperature
input transition rise and fall rate
pin nOE; V
CC
= 2.3 V to 3.6 V
control inputs
enable and disable mode
Conditions
Min
2.3
0
0
40
0
Max
3.6
3.6
V
CC
+125
200
Unit
V
V
V
C
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
V
IL
I
I
I
S(OFF)
HIGH-level
input voltage
Conditions
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
T
amb
=
40 C
to +85
C
Min
1.7
2.0
-
-
-
-
Typ
[1]
-
-
-
-
-
-
Max
-
-
0.7
0.9
1.0
1
T
amb
=
40 C
to +125
C
Unit
Min
1.7
2.0
-
-
-
-
Max
-
-
0.7
0.9
20
20
V
V
V
V
A
A
LOW-level input V
CC
= 2.3 V to 2.7 V
voltage
V
CC
= 3.0 V to 3.6 V
input leakage
current
pin nOE; V
I
= GND to V
CC
;
V
CC
= 3.6 V
OFF-state
V
CC
= 3.6 V; see
Figure 6
leakage current
74CBTLV3125
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 4 — 9 November 2016
4 of 18
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