CCG1 Datasheet
USB Type-C Port Controller with Power
Delivery
General Description
CCG1 provides a complete USB Type-C and USB Power Delivery port control solution. The core architecture of CCG1 enables a
base Type-C solution that can scale to a complete 100-W USB Power Delivery with Alternate Mode multiplex support. CCG1 is also
a Type-C cable ID IC for active and passive cables. The CCG1 controller detects connector insert, plug orientation and VCONN
switching signals. CCG1 makes it easier to add USB Power Delivery to any architecture because it provides control signals to manage
external VBUS and V
CONN
power management solutions and external mux controls for most single cable-docking solutions.
The CCG1 family of devices are fixed-function parts that use a configuration table to control their operation in different applications.
The functionality is implemented in firmware and will be certified against USB Implementers Forum (USB-IF) compliance tests when
available. The programmability allows CCG1 devices to track any USB Specification changes. For information on accessing the source
code, contact
Cypress support.
Applications
■
■
Type-C Support
■
■
■
Notebooks, tablets, monitors, docking stations
Power adapters, USB Type-C cables
Features
32-bit MCU Subsystem
■
Integrated transceiver (BB PHY)
Supports up to two USB ports with PD
Supports routing of all protocols through an external mux
Supports Provider and Consumer roles
Supports all power profiles
3.2 V to 5.5 V operation
Sleep 1.3 mA, Deep Sleep 1.3
A
[1]
40-pin QFN
16-pin SOIC
35-ball wafer-level CSP (WLCSP)
PD Support
■
■
48-MHz ARM Cortex-M0 CPU with 32-KB flash and 4-KB
SRAM
Low-Power Operation
■
■
Integrated analog blocks
12-bit, 1-Msps ADC for VBUS voltage and current monitoring
■
Dynamic overcurrent and overvoltage protection
■
Packages
■
■
■
Integrated digital blocks
Two configurable 16-bit TCPWM blocks
2
■
One I C master or slave
■
Figure 1. CCG1 Block Diagram
[2, 3, 4, 5, 6, 7]
Notes
1. Values measured for CCG1 silicon only. Application specific power numbers may be higher.
2. Timer, counter, pulse-width modulation block.
3. Serial communication block configurable as I
2
C.
4. Base band.
5. Termination resistor denoting a Downstream Facing Port (DFP).
6. Termination resistor denoting a Upstream Facing Port (UFP).
7. Termination resistor denoting an Electronically Marked Cable Assembly (EMCA).
Cypress Semiconductor Corporation
Document Number: 001-93639 Rev. *K
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 3, 2017
CCG1 Datasheet
Contents
Functional Definition ........................................................ 3
CPU and Memory Subsystem ..................................... 3
System Resources ...................................................... 3
GPIO ........................................................................... 3
Pin Definitions .................................................................. 4
Pinouts ............................................................................ 10
Power ............................................................................... 11
Electrical Specifications ................................................ 12
Absolute Maximum Ratings ....................................... 12
Device-Level Specifications ...................................... 12
Digital Peripherals ..................................................... 14
Memory ..................................................................... 15
System Resources .................................................... 16
Applications in Detail ..................................................... 18
Ordering Information ...................................................... 23
Ordering Code Definitions ......................................... 23
Packaging ........................................................................ 24
Acronyms ........................................................................ 27
Document Conventions ................................................. 28
Units of Measure ....................................................... 28
Revision History ............................................................. 29
Sales, Solutions, and Legal Information ...................... 31
Worldwide Sales and Design Support ....................... 31
Products .................................................................... 31
PSoC® Solutions ...................................................... 31
Cypress Developer Community ................................. 31
Technical Support ..................................................... 31
Document Number: 001-93639 Rev. *K
Page 2 of 31
CCG1 Datasheet
FIFO for receive and transmit which, by increasing the time given
for the CPU to read data, greatly reduces the need for clock
stretching caused by the CPU not having read data on time.
The I
2
C peripheral is compatible with the I
2
C Standard-mode,
Fast-mode, and Fast-mode Plus devices, as defined in the NXP
I
2
C-bus specification and user manual (UM10204). The I
2
C bus
I/O is implemented with GPIO in open-drain modes.
The CCG1 is not completely compliant with the I
2
C spec in the
following respects:
■
Functional Definition
CPU and Memory Subsystem
CPU
The Cortex-M0 CPU in the CCG1 is part of the 32-bit MCU
subsystem, which is optimized for low-power operation with
extensive clock gating. It mostly uses 16-bit instructions and
executes a subset of the Thumb-2 instruction set. This enables
fully compatible binary upward migration of the code to higher
performance processors such as the Cortex-M3 and M4, thus
enabling upward compatibility. The Cypress implementation
includes a hardware multiplier that provides a 32-bit result in one
cycle. It includes a nested vectored interrupt controller (NVIC)
block with 32 interrupt inputs and a Wakeup Interrupt Controller
(WIC). The WIC can wake the processor up from the Deep Sleep
mode, allowing power to be switched off to the main processor
when the chip is in the Deep Sleep mode. The Cortex-M0 CPU
provides a Non-Maskable Interrupt (NMI) input, which is made
available to the user when it is not in use for system functions
requested by the user.
The CPU also includes a debug interface, the serial wire debug
(SWD) interface, which is a 2-wire form of JTAG; the debug
configuration used for CCG1 has four break-point (address)
comparators and two watchpoint (data) comparators.
Flash
The CCG1 device has a flash module with a flash accelerator,
tightly coupled to the CPU to improve average access times from
the flash block. The flash block is designed to deliver 1 wait-state
(WS) access time at 48 MHz and 0-WS access time at 24 MHz.
The flash accelerator delivers 85% of single-cycle SRAM access
performance on average. Part of the flash module can be used
to emulate EEPROM operation if required.
SROM
A supervisory ROM that contains boot and configuration routines
is provided.
GPIO cells are not overvoltage tolerant and, therefore, cannot
be hot-swapped or powered up independently of the rest of the
I
2
C system.
Fast-mode Plus has an I
OL
specification of 20 mA at a V
OL
of
0.4 V. The GPIO cells can sink a maximum of 8 mA I
OL
with a
V
OL
maximum of 0.6 V.
Fast-mode and Fast-mode Plus specify minimum Fall times,
which are not met with the GPIO cell; Slow strong mode can
help meet this spec depending on the Bus Load.
When the SCB is an I
2
C Master, it interposes an IDLE state
between NACK and Repeated Start; the I
2
C spec defines Bus
free as following a Stop condition so other Active Masters do
not intervene but a Master that has just become activated may
start an Arbitration cycle.
When the SCB is in the I
2
C Slave mode, and Address Match
on External Clock is enabled (EC_AM = 1) along with operation
in the internally clocked mode (EC_OP = 0), then its I
2
C
address must be even.
■
■
■
■
GPIO
The CCG1 has up to 30 GPIOs, which are configured for various
functions. Refer to the pinout tables for the definitions. The GPIO
block implements the following:
■
System Resources
Power System
The power system is described in detail in the section
Power on
page 11.
It provides assurance that voltage levels are as required
for each respective mode and either delay mode entry (on
power-on reset (POR), for example) until voltage levels are as
required for proper function or generate resets (Brown-Out
Detect (BOD)) or interrupts (Low Voltage Detect (LVD)). The
CCG1 operates with a single external supply over the range of
3.2 V to 5.5 V operation and has three different power modes:
Active, Sleep, and Deep Sleep; transitions between modes are
managed by the power system.
Serial Communication Blocks (SCB)
The CCG1 has one SCB, which can implement an I
2
C interface.
The hardware I
2
C block implements a full multi-master and slave
interface (it is capable of multimaster arbitration). This block is
capable of operating at speeds of up to 1 Mbps (Fast Mode Plus)
and has flexible buffering options to reduce interrupt overhead
and latency for the CPU. It also supports EZ-I
2
C that creates a
mailbox address range in the memory of the CCG1 and effec-
tively reduces I
2
C communication to reading from and writing to
an array in memory. In addition, the block supports an 8-deep
Document Number: 001-93639 Rev. *K
Eight drive strength modes:
❐
Analog input mode (input and output buffers disabled)
❐
Input only
❐
Weak pull-up with strong pull-down
❐
Strong pull-up with weak pull-down
❐
Open drain with strong pull-down
❐
Open drain with strong pull-up
❐
Strong pull-up with strong pull-down
❐
Weak pull-up with weak pull-down
Input threshold select (CMOS or LVTTL).
Individual control of input and output buffer enabling/disabling
in addition to the drive strength modes.
Hold mode for latching previous state (used for retaining I/O
state in Deep Sleep mode).
Selectable slew rates for dV/dt related noise control to improve
EMI.
■
■
■
■
During power-on and reset, the I/O pins are forced to the disable
state so as not to crowbar any inputs and/or cause excess
turn-on current. A multiplexing network, known as a high-speed
I/O matrix, is used to multiplex between various signals that may
connect to an I/O pin.
Page 3 of 31
CCG1 Datasheet
Pin Definitions
Table 1
provides the pin definition for 35-Ball WLCSP for the Cable/EMCA application. Refer to
Table 23
for part numbers to package
mapping.
Table 1. Pin Definitions for 35-ball WLCSP for EMCA Cable Application
Functional Pin Name
CYPD1103-
35FNXIT
Balls
C4
D7
D1
C1
B1
B2
B6
A7
C7
B7
C5
B3
B5
D3
A3
D4
E4
Type
CC1 control
0: TX enabled
z: RX sense
Configuration Channel 1
SWD I/O
SWD clock
I
2
C clock signal
I
2
C data signal
Reset
Regulated digital supply output. Connect a 1 to 1.6-µF capacitor. No
external source should be connected
Power supply for both analog and digital sections
Analog ground
Data reference signal for CC lines
Signals for internal use only. The TX_U output signal should be
connected to the TX_M signal
–
Reference signal for internal use. Connect to TX_REF output via a
2.4K 1% resistor
Connect to GND via 2K 1% resistor
Reference signal generated by connecting internal current source to
two 1K external resistors
Optional control signal to remove RA after assertion of VCONN
0: RA disconnected
1: RA connected
Local VCONN detection signal
0: VCONN is not locally applied
1: VCONN is locally applied
Reference signal for internal use. Connect to the output of resistor
divider from VDDD.
Optional control signal to remove RA after assertion of VCONN (NC
for 2 chip/cable)
0: RA disconnected
1: RA connected
Bypass capacitor for internal analog circuits
Configuration channel 1 RX signal for Low Power States
General-purpose I/Os
Description
CC1_RX
CC1_TX
SWD_IO
SWD_CLK
I2C_SCL
I2C_SDA
XRES
VCCD
VDDD
VSSA
CC_VREF
TX_U
TX_M
TX_REF_IN
TX_GND
TX_REF_OUT
RA_DISCONNECT
I
O
I/O
I
I/O
I/O
I
POWER
POWER
GND
I
O
I
I
I
O
O
VCONN_DET
CC1_LPREF
C6
A5
I
I
RA_FAR_DISCONNECT
BYPASS
CC1_LPRX
GPIO
E5
D5
C3
A1, A2, A4, A6,
B4, C2, D2, D6,
E1, E2, E3, E6,
E7
O
I
I
–
Document Number: 001-93639 Rev. *K
Page 4 of 31
CCG1 Datasheet
Table 2
provides the pin definitions for 40-pin QFN and 35-ball WLCSP for the notebook, tablet, smartphone, and monitor
applications. Refer to
Table 23
on page 23
for part numbers to package mapping.
Table 2. Pin Definitions for 40-QFN and 35-ball WLCSP for Notebook, Tablet, SmartPhone and Monitor Applications
Functional Pins
CYPD
CYPD
CYPD
1122-40LQXI 1121-40LQXI 1131-35FNXIT
Pins
[8]
Pins
[9]
Balls
[10]
Type
Description
MUXSEL_1
MUXSEL_2
CC1_CTRL
1
2
3
1
2
3
D5
D6
D3
O
O
I/O
External Data Mux Select signal 1
External Data Mux Select signal 2
CC1 control
0: TX enabled
z: RX sense
CC2 control
0: TX enabled
z: RX sense
External Data Mux Select signal 3
External Data Mux Select signal 4
Current Sensing Plus input
Current Sensing Minus input I
Ground
Configuration Channel 1
CC Reference Select signal
SWD IO
SWD Clock
HotPlug Detection for Display Port Alternate Mode
General-purpose I/O
Voltage Select signal 2 for selecting output voltage
General-purpose I/O
General-purpose I/O
Current Fault Indication
0: No fault
1: Current fault
I2C Clock signal
I2C Data signal
I2C Interrupt
CC Reference Select signal
Open Drain signal to connect RD to CC 1 line
z: RD not connected
0: RD connected for Monitor application
1: RD connected for Notebook application
Open Source signal to connect RP to CC 1 line
z: RP not connected
1: RP connected
CC2_CTRL
MUXSEL_3
MUXSEL_4
CS_P
CS_M
VSS
CC1
CC_SEL_REF_1
SWD_IO
SWD_CLK
HOTPLUG_DET
GPIO1
VSEL2
GPIO2
GPIO3
IFAULT
I2C_SCL
I2C_SDA
I2C_INT
CC_SEL_REF_2
4
5
6
7
8
9
10
11
12
13
14
15
–
16
17
–
18
19
20
21
4
5
6
7
8
9
10
11
12
13
14
–
15
–
–
17
18
19
20
21
E4
E5
E6
E3
E2
–
-
E1
D1
C1
C2
–
–
–
–
–
B1
B2
A2
A1
I/O
O
O
I
I
GND
I/O
O
I/O
I
I/O
I/O
O
I/O
I/O
I
I/O
I/O
O
O
CC1_RD
22
22
C3
O
CC1_RP
23
23
A5
O
Notes
8. Pinout for Notebook DRP application for 40-QFN.
9. Pinout for Monitor DRP application for 40-QFN.
10. Pinout for Notebook DRP application for 35-CSP.
Document Number: 001-93639 Rev. *K
Page 5 of 31
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
