MIC26903-ZA
28V, 9A Hyper Speed Control
Synchronous DC-to-DC Buck Regulator
SuperSwitcher™ II
General Description
The Micrel MIC26903-ZA is a constant-frequency,
synchronous buck regulator featuring a unique adaptive
on-time control architecture. The MIC26903-ZA operates
over an input supply range of 4.5V to 28V and provides a
regulated output of up to 9A of output current. The output
voltage is adjustable down to 0.6V with a guaranteed
accuracy of ±1%, and the device operates at a switching
frequency of 600kHz.
Micrel’s Hyper Speed Control architecture allows for
ultra-fast transient response while reducing the output
capacitance and also makes (High V
IN
)/(Low V
OUT
)
operation possible. This adaptive t
ON
ripple control
architecture combines the advantages of fixed-frequency
operation and fast transient response in a single device.
The MIC26903-ZA offers a full suite of features to ensure
protection of the IC during fault conditions. These include
undervoltage lockout to ensure proper operation under
power-sag conditions, internal soft-start to reduce inrush
current, foldback current limit, “hiccup mode” short-circuit
protection, and thermal shutdown. An open-drain Power
Good (PG) pin is provided.
Datasheets and support documentation are available on
Micrel’s web site at:
www.micrel.com.
SuperSwitcher™ II
Features
Hyper Speed Control architecture enables
High Delta V operation (V
IN
= 28V and V
OUT
= 0.6V)
Small output capacitance
4.5V to 28V voltage input
9A output current capability and 95% peak efficiency
Adjustable output from 0.6V to 5.5V
±1% feedback accuracy
Any Capacitor stable
-
zero-to-high ESR
600kHz switching frequency
No external compensation
Power Good (PG) output
Foldback I-limit and “hiccup” short-circuit protection
Supports safe startup into a pre-biased load
–40°C to +125°C junction temperature range
28-pin 5mm × 6mm QFN package
Applications
Distributed POL and telecom/networking infrastructure
Printers, scanners, graphic and video cards
Set-top boxes, gateways and routers
Typical Application
Efficiency (V
IN
= 12V)
vs. Output Current
100
95
90
5.0V
3.3V
2.5V
1.8V
1.5V
1.2V
1.0V
0.9V
EFFICIENCY (%)
85
80
75
70
65
60
55
50
0
2
4
6
8
10
V
IN
= 12V
12
OUTPUT CURRENT (A)
Hyper Speed Control, SuperSwitcher II, and Any Capacitor are trademarks of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 •
http://www.micrel.com
July 22, 2014
Revision 1.1
Micrel, Inc.
MIC26903-ZA
Ordering Information
Part Number
MIC26903-ZAYJL
Voltage
Adjustable
Switching
Frequency
600kHz
Package
28-Pin 5mm
×
6mm QFN
Junction Temperature
Range
–40°C to +125°C
Lead
Finish
Pb-Free
Pin Configuration
28-Pin 5mm
×
6mm QFN (JL)
(Top View)
Pin Description
Pin Number
1
Pin Name
PVDD
Pin Function
5V Internal Linear Regulator output: PVDD supply is the power MOSFET gate drive supply voltage
created by internal LDO from VIN. When VIN
<
+5.5V, PVDD should be tied to the PVIN pins. A 2.2µF
ceramic capacitor from the PVDD pin to PGND (pin 2) must be placed next to the IC.
Power Ground: PGND is the ground path for the buck converter power stage. The PGND pins connect
to the low-side N-Channel internal MOSFET gate drive supply ground, the sources of the MOSFETs,
the negative terminals of input capacitors, and the negative terminals of output capacitors. The loop
for the power ground should be as small as possible and separate from the signal ground (SGND)
loop.
No Connect.
Switch Node output: Internal connection for the high-side MOSFET source and low-side MOSFET
drain. Because of the high-speed switching on this pin, the SW pin should be routed away from
sensitive nodes.
High-Side N-Internal MOSFET Drain Connection input: The PVIN operating voltage range is from 4.5V
to 28V. Input capacitors between the PVIN pins and the power ground (PGND) are required and keep
the connection short.
Boost output: Bootstrapped voltage to the high-side N-channel MOSFET driver. A Schottky diode is
connected between the PVDD pin and the BST pin. A boost capacitor of 0.1μF is connected between
the BST pin and the SW pin. Adding a small resistor at the BST pin can reduce the turn-on time of
high-side N-Channel MOSFETs.
2, 5, 6,
7, 8, 21
PGND
3
4, 9,
10, 11, 12
13,14,15,
16,17,18,19
NC
SW
PVIN
20
BST
July 22, 2014
2
Revision 1.1
Micrel, Inc.
MIC26903-ZA
Pin Description (Continued)
Pin Number
Pin Name
Pin Function
Current Sense input: The CS pin senses current by monitoring the voltage across the low-side
MOSFET during the OFF-time. The current sensing is necessary for short circuit protection. To sense
the current accurately, connect the low-side MOSFET drain to SW using a Kelvin connection. The CS
pin is also the high-side MOSFET’s output driver return.
Signal Ground: SGND must be connected directly to the ground planes. Do not route the SGND pin to
the PGND pad on the top layer (see “PCB
Layout Guidelines”
for details).
Feedback input: Input to the transconductance amplifier of the control loop. The FB pin is regulated to
0.6V. A resistor divider connecting the feedback to the output is used to adjust the desired output
voltage.
Power Good output: Open drain output. The PG pin is externally tied with a resistor to VDD. A high
output is asserted when V
OUT
>
92% of nominal.
Enable input: A logic level control of the output. The EN pin is CMOS-compatible. Logic high = enable,
logic low = shutdown. In the off state, the supply current of the device is greatly reduced (typically
5µA). Do not leave the EN pin open.
Power Supply Voltage input: Requires a bypass capacitor to SGND.
5V Internal Linear Regulator output: VDD supply is the power MOSFET gate drive supply voltage and
the supply bus for the IC. VDD is created by internal LDO from VIN. When VIN
<
+5.5V, VDD should
be tied to PVIN pins. A 1µF ceramic capacitor from the VDD pin to SGND pins must be placed next to
the IC.
22
CS
23
SGND
24
FB
25
PG
26
27
EN
VIN
28
VDD
July 22, 2014
3
Revision 1.1
Micrel, Inc.
MIC26903-ZA
Absolute Maximum Ratings
(1)
PVIN to PGND...............................................
−0.3V
to +29V
VIN to PGND .................................................
−0.3V
to PVIN
PVDD, VDD to PGND .....................................
−0.3V
to +6V
V
SW
, V
CS
to PGND .............................
−0.3V
to (PVIN +0.3V)
V
BST
to V
SW
........................................................
−0.3V
to 6V
V
BST
to PGND ..................................................
−0.3V
to 35V
V
FB
, V
PG
to PGND .............................
−0.3V
to (VDD + 0.3V)
V
EN
to PGND .......................................
−0.3V
to (VIN +0.3V)
PGND to SGND............................................
−0.3V
to +0.3V
Junction Temperature .............................................. +150°C
Storage Temperature (T
S
) .........................
−65°C
to +150°C
Lead Temperature (soldering, 10s) ............................ 260°C
(4)
ESD Rating ................................................. ESD Sensitive
Operating Ratings
(2)
Supply Voltage (PVIN, VIN) .............................. 4.5V to 28V
PVDD, VDD Supply Voltage ............................ 4.5V to 5.5V
Enable Input (V
EN
) ................................................. 0V to VIN
Junction Temperature (T
J
) ........................
−40°C
to +125°C
Maximum Power Dissipation ......................................
Note 3
(3)
Package Thermal Resistance
5mm × 6mm QFN (θ
JA
) ..................................... 28°C/W
Electrical Characteristics
(5)
PVIN = VIN = V
EN
= 12V, V
BST
– V
SW
= 5V; T
A
= 25°C, unless noted.
Bold
values indicate
−40°C
≤ T
J
≤+125°C.
Parameter
Power Supply Input
Input Voltage Range (VIN, PVIN)
Quiescent Supply Current
Shutdown Supply Current
VDD Supply Voltage
VDD Output Voltage
VDD UVLO Threshold
VDD UVLO Hysteresis
Dropout Voltage (VIN – VDD)
DC-to-DC Controller
Output Voltage Adjust Range (V
OUT
)
Reference
Feedback Voltage
Load Regulation
Line Regulation
FB Bias Current
Notes:
1. Exceeding the absolute maximum ratings may damage the device.
2. The device is not guaranteed to function outside its operating ratings.
3. PD
(MAX)
= (T
J(MAX)
– T
A
)/
θ
JA
, where
θ
JA
depends upon the printed circuit layout. A 5-in
2
4 layer, 0.62”, FR-4 PCB with 2oz finish copper weight per
layer is used for the
θ
JA
.
4. Devices are ESD sensitive. Handling precautions are recommended. Human body model, 1.5kΩ in series with 100pF.
5. Specification for packaged product only.
Condition
Min.
Typ.
Max.
Units
4.5
V
FB
= 1.5V (non-switching)
V
EN
= 0V
730
5
28
1500
10
V
µA
µA
VIN = 7V to 28V, I
DD
= 40mA
VDD Rising
4.8
3.7
5
4.2
400
5.4
4.5
V
V
mV
I
DD
= 25mA
−40°C ≤
T
J
≤
85°C
0°C
≤
T
J
≤
85°C, ±1.0%
−40°C ≤
T
J
≤ 125°C, ±1.5%
I
OUT
= 0A to 9A
VIN = 4.5V to 28V
V
FB
= 0.6V
380
600
mV
0.6
5.5
V
0.594
0.591
0.6
0.6
0.25
0.25
50
0.606
0.609
V
%
%
nA
July 22, 2014
4
Revision 1.1
Micrel, Inc.
MIC26903-ZA
Electrical Characteristics
(5)
(Continued)
PVIN = VIN = V
EN
= 12V, V
BST
– V
SW
= 5V; T
A
= 25°C, unless noted.
Bold
values indicate
−40°C
≤ T
J
≤ +125°C.
Parameter
Enable Control
EN Logic Level High
EN Logic Level Low
EN Bias Current
Oscillator
Switching Frequency
(6)
(7)
Condition
Min.
Typ.
Max.
Units
1.8
0.6
V
EN
= 12V
6
30
V
V
µA
450
V
FB
= 0V
V
FB
= 1.0V
600
82
0
300
750
kHz
%
%
ns
Maximum Duty Cycle
Minimum Duty Cycle
Minimum OFF-Time
Soft-Start
Soft-Start Time
5
ms
A
A
A
Short-Circuit Protection
Current-Limit Threshold
Current-Limit Threshold
Short-Circuit Current
Internal FETs
Top-MOSFET R
DS (ON)
Bottom-MOSFET R
DS (ON)
SW Leakage Current
V
IN
Leakage Current
Power Good (PG)
PG Threshold Voltage
PG Hysteresis
PG Delay Time
PG Low Voltage
Thermal Protection
Overtemperature Shutdown
Overtemperature Shutdown Hysteresis
Notes:
6. Measured in test mode.
7. The maximum duty-cycle is limited by the fixed mandatory OFF-time t
OFF
, typically 300ns.
V
FB
= 0.6V, T
J
= 25°C
V
FB
= 0.6V, T
J
= 125°C
V
FB
= 0V
I
SW
= 3A
I
SW
= 3A
V
EN
= 0V
V
EN
= 0V
12.5
11.25
15
15
4
20
20
27
10.5
60
25
mΩ
mΩ
µA
µA
Sweep V
FB
from Low-to-High
Sweep V
FB
from High-to-Low
Sweep V
FB
from Low-to-High
Sweep V
FB
<
0.9
×
V
NOM
, I
PG
= 1mA
85
92
5.5
100
70
95
%V
OUT
%V
OUT
µs
200
mV
°C
°C
T
J
Rising
160
15
July 22, 2014
5
Revision 1.1
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