INTEGRATED CIRCUITS
74ALVT16652
2.5V/3.3V 16-bit bus transceiver/register
(3-State)
Product specification
Supersedes data of 1996 Aug 13
IC23 Data Handbook
1998 Feb 13
Philips
Semiconductors
Philips Semiconductors
Product specification
2.5V/3.3V 16-bit bus transceiver/register
(3-State)
74ALVT16652
FEATURES
•
16–bit bus interface
•
5V I/O Compatible
•
3-State buffers
•
Output capability: +64mA/-32mA
•
TTL input and output switching levels
•
Input and output interface capability to systems at 5V supply
•
Bus-hold data inputs eliminate the need for external pull-up
•
Live insertion/extraction permitted
•
Power-up reset
•
Power-up 3-State
•
No bus current loading when output is tied to 5V bus
•
Latch-up protection exceeds 500mA per JEDEC JC40.2 Std 17
•
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
resistors to hold unused inputs
DESCRIPTION
The 74ALVT16652 is a high-performance BiCMOS product
designed for V
CC
operation at 2.5V or 3.3V with I/O compatibility up
to 5V. The device can be used as two 8-bit transceivers or one
16-bit transceiver.
Complimentary output-enable (OEAB and OEBA) inputs are
provided to control the transceiver functions. Select-control (SAB
and SBA) inputs are provided to select whether real-time or stored
data is transferred. A Low-input level selects real-time data, and a
High input level selects stored data. The circuitry used for select
control eliminates the typical decoding glitch that occurs in a
multiplexer during the transition between stored and real-time data.
Data on the A or B bus, or both, can be stored in the internal
flip-flops by Low-to-High transitions at the appropriate clock (CPAB
or CPBA) inputs regardless of the levels on the select-control or
output-enable inputs. When SAB and SBA are in real-time transfer
mode, it is possible to store data without using the internal D-type
flip-flops by simultaneously enabling OEAB and OEBA. In this
configuration, each output reinforces its input. Thus, when all other
data sources to the two sets of bus lines are at high impedance,
each set of bus lines remains at its last level configuration.
CONDITIONS
T
amb
= 25°C
C
L
= 50pF
V
I
= 0V or V
CC
V
I/O
= 0V or V
CC
Outputs disabled
TYPICAL
2.5V
2.0
2.1
3
9
40
3.3V
1.5
1.6
3
9
70
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
I/O
I
CCZ
PARAMETER
Propagation delay
nAx to nBx or nBx to nAx
Input capacitance DIR, OE
I/O pin capacitance
Total supply current
UNIT
ns
pF
pF
µA
ORDERING INFORMATION
PACKAGES
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ALVT16652 DL
74ALVT16652 DGG
NORTH AMERICA
AV16652 DL
AV16652 DGG
DWG NUMBER
SOT371-1
SOT364-1
LOGIC SYMBOL (IEEE/IEC)
56
1
55
54
2
3
EN1(BA)
EN2(AB)
C3
G4
C5
G6
52
29
28
30
31
27
26
EN7(BA)
EN8(AB)
C9
G10
C11
G12
42
5
w1
1
5D
6
4
4
3D
1
15
w1
7
11D 12
1 12
10 9D
10 1
w1
8
w1
2
51
49
48
47
45
44
43
16
17
19
20
21
23
24
1 6
6
8
9
10
12
13
14
41
40
38
37
36
34
33
SW00158
1998 Feb 13
2
853-1854 18962
Philips Semiconductors
Product specification
2.5V/3.3V 16-bit bus transceiver/register
(3-State)
74ALVT16652
PIN CONFIGURATION
1OEAB
1CPAB
1SAB
GND
1A0
1A1
V
CC
1A2
1A3
1A4
GND
1A5
1A6
1A7
2A0
2A1
2A2
GND
2A3
2A4
2A5
V
CC
2A6
2A7
GND
2SAB
2CPAB
20EAB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OEBA
1CPBA
1SBA
GND
1B0
1B1
V
CC
1B2
1B3
1B4
GND
1B5
1B6
1B7
2B0
2B1
2B2
GND
2B3
2B4
2B5
V
CC
2B6
2B7
GND
2SBA
2CPBA
2OEBA
LOGIC SYMBOL
5
6
8
9
10
12 13
14
1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7
2
3
54
55
1CPAB
1SAB
1SBA
1CPBA
1AB 1B1 1B2 1B3 1B4 1B5 1B6 1B7
1OEAB
1OEBA
1
56
52
15
51
16
49
17
48 47
19 20
45 44
21 23
43
24
2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7
27
26
31
30
2CPAB
2SAB
2SBA
2CPBA
2AB 2B1 2B2 2B3 2B4 2B5 2B6 2B7
2OEAB
2OEBA
28
29
42
41
40
38 37
36
34
33
SH00046
SW00159
PIN DESCRIPTION
PIN NUMBER
2, 55, 27, 30
3, 54, 26, 31
5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24
52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33
1, 56, 28, 29
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
SYMBOL
1CPAB, 1CPBA, 2CPAB, 2CPBA
1SAB, 1SBA, 2SAB, 2SBA
1A0 – 1A7,
2A0 – 2A7
1B0 – 1B7,
2B0 – 2B7
1OEAB, 1OEBA,
2OEAB, 2OEBA
GND
V
CC
NAME AND FUNCTION
Clock input A to B / Clock input B to A
Select input A to B / Select input B to A
Data inputs/outputs (A side)
Data inputs/outputs (B side)
Output enable inputs
Ground (0V)
Positive supply voltage
1998 Feb 13
3
Philips Semiconductors
Product specification
2.5V/3.3V 16-bit bus transceiver/register
(3-State)
74ALVT16652
LOGIC DIAGRAM
nOEBA
nOEAB
nCPBA
nSBA
nCPAB
nSAB
1of 8 Channels
1D
C1
Q
nA0
1D
C1
Q
nB0
nA1
nA2
nA3
nA4
nA5
nA6
nA7
DETAIL A X 7
nB1
nB2
nB3
nB4
nB5
nB6
nB7
SH00065
FUNCTION TABLE
INPUTS
nOEAB
L
L
X
H
L
L
L
L
H
H
H
H
L
X
↑
*
**
=
=
=
=
nOEBA
H
H
H
H
X
L
L
L
H
H
L
nCPAB
H or L
↑
↑
↑
H or L
↑
X
X
X
H or L
H or L
nCPBA
H or L
↑
H or L
↑
↑
↑
X
H or L
X
X
H or L
nSAB
X
X
X
**
X
X
X
X
L
H
H
nSBA
X
X
X
X
X
**
L
H
X
X
H
nAx
Input
Input
Unspecified
output*
Output
Input
Output
DATA I/O
nBx
Input
Unspecified
output*
Input
Input
Output
Output
OPERATING MODE
Isolation
Store A and B data
Store A, Hold B
Store A in both registers
Hold A, Store B
Store B in both registers
Real time B data to A bus
Stored B data to A bus
Real time A data to B bus
Store A data to B bus
Stored A data to B bus
Stored B data to A bus
High voltage level
Low voltage level
Don’t care
Low-to-High clock transition
The data output function may be enabled or disabled by various signals at the nOEBA and nOEAB inputs. Data input functions are
always enabled, i.e., data at the bus pins will be stored on every Low-to-High transition of the clock.
If both Select controls (nSAB and nSBA) are Low, then clocks can occur simultaneously. If either Select control is High, the clocks must
be staggered in order to load both registers.
1998 Feb 13
4
Philips Semiconductors
Product specification
2.5V/3.3V 16-bit bus transceiver/register
(3-State)
74ALVT16652
The following examples demonstrate the four fundamental
bus-management functions that can be performed with the
74ALVT16652. The select pins determine whether data is stored or
transferred through the device in real time. The output enable pins
determine the direction of the data flow.
REAL TIME BUS TRANSFER
BUS B TO BUS A
REAL TIME BUS TRANSFER
BUS A TO BUS B
STORAGE FROM
A, B, OR A AND B
A
B
A
B
A
B
nOEAB nOEBA nCPAB nCPBA nSAB nSBA
L
L
X
X
X
L
}
A
1998 Feb 13
nOEAB nOEBA nCPAB nCPBA nSAB nSBA
H
H
X
X
L
X
TRANSFER STORED DATA
TO A OR B
nOEAB nOEBA nCPAB nCPBA nSAB nSBA
H
L
H|L
H|L
H
H
}
L
L
X
H
nOEAB nOEBA nCPAB nCPBA nSAB nSBA
X
H
↑
X
X
X
X
↑
↑
↑
X
X
X
X
}
B
}
SH00066
5
GD32 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
