AUTOMOTIVE GRADE
Features
Advanced Plannar Technology
Logic-Level Gate Drive
Low On-Resistance
175°C Operating Temperature
Fast Switching
Fully Avalanche Rated
Repetitive Avalanche Allowed up to Tjmax
Lead-Free, RoHS Compliant
Automotive Qualified *
AUIRLR3915
HEXFET
®
Power MOSFET
V
DSS
R
DS(on)
typ.
max.
I
D (Silicon Limited)
I
D (Package Limited)
55V
12m
14m
61A
30A
D
Description
Specifically designed for Automotive applications, this Stripe Planar
design of HEXFET® Power MOSFETs utilizes the latest
processing techniques to achieve low on-resistance per silicon
area. This benefit combined with the fast switching speed and
ruggedized device design that HEXFET power MOSFETs are well
known for, provides the designer with an extremely efficient and
reliable device for use in Automotive and a wide variety of other
applications.
Base part number
AUIRLR3915
Package Type
D-Pak
G
S
D-Pak
AUIRLR3915
G
Gate
D
Drain
S
Source
Standard Pack
Form
Quantity
Tube
75
Tape and Reel Left
3000
Orderable Part Number
AUIRLR3915
AUIRLR3915TRL
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress
ratings only; and functional operation of the device at these or any other condition beyond those indicated in the specifications is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The thermal resistance
and power dissipation ratings are measured under board mounted and still air conditions. Ambient temperature (TA) is 25°C, unless
otherwise specified.
Symbol
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
D
@ T
C
= 25°C
I
DM
P
D
@T
C
= 25°C
V
GS
E
AS
E
AS
(Tested)
I
AR
E
AR
T
J
T
STG
Parameter
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
Continuous Drain Current, V
GS
@ 10V (Package Limited)
Pulsed Drain Current
Maximum Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy (Thermally Limited)
Single Pulse Avalanche Energy Tested Value
Avalanche Current
Repetitive Avalanche Energy
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds (1.6mm from case)
Max.
61
43
30
240
120
0.77
± 16
200
600
See Fig.15,16, 12a, 12b
-55 to + 175
Units
A
W
W/°C
V
mJ
A
mJ
°C
300
Thermal Resistance
Symbol
R
JC
R
JA
R
JA
Parameter
Junction-to-Case
Junction-to-Ambient ( PCB Mount)
Junction-to-Ambient
Typ.
–––
–––
–––
Max.
1.3
50
110
Units
°C/W
HEXFET® is a registered trademark of Infineon.
*Qualification
standards can be found at
www.infineon.com
1
2015-12-14
Static @ T
J
= 25°C (unless otherwise specified)
V
(BR)DSS
V
(BR)DSS
/T
J
R
DS(on)
V
GS(th)
gfs
I
DSS
I
GSS
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Trans conductance
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Internal Drain Inductance
Internal Source Inductance
AUIRLR3915
Min. Typ. Max. Units
Conditions
55
––– –––
V V
GS
= 0V, I
D
= 250µA
––– 0.057 ––– V/°C Reference to 25°C, I
D
= 1mA
–––
12
14
V
GS
= 10V, I
D
= 30A
m
–––
14
17
V
GS
= 5.0V, I
D
= 26A
1.0
–––
3.0
V V
DS
= V
GS
, I
D
= 250µA
42
––– –––
S V
DS
= 25V, I
D
= 30A
––– –––
20
V
DS
= 55V, V
GS
= 0V
µA
––– ––– 250
V
DS
= 55V,V
GS
= 0V,T
J
=125°C
––– ––– 200
V
GS
= 16V
nA
––– ––– -200
V
GS
= -16V
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Min.
–––
–––
–––
–––
–––
61
9.0
17
7.4
51
83
100
4.5
7.5
1870
390
74
2380
290
540
92
14
25
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
I
D
= 30A
nC
V
DS
= 44V
V
GS
= 10V
V
DD
= 28V
I
D
= 30A
ns
R
G
= 8.5
V
GS
= 10V
Between lead,
6mm (0.25in.)
nH
from package
and center of die contact
V
GS
= 0V
V
DS
= 25V
ƒ = 1.0MHz, See Fig. 5
pF
V
GS
= 0V, V
DS
= 1.0V ƒ = 1.0MHz
V
GS
= 0V, V
DS
= 44V ƒ = 1.0MHz
V
GS
= 0V, V
DS
= 0V to 44V
Conditions
MOSFET symbol
showing the
A
integral reverse
p-n junction diode.
V T
J
= 25°C,I
S
= 30A, V
GS
= 0V
ns T
J
= 25°C ,I
F
= 30A, V
DD
= 25V
nC di/dt = 100A/µs
Dynamic Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
D
L
S
C
iss
Input Capacitance
C
oss
Output Capacitance
C
rss
Reverse Transfer Capacitance
C
oss
Output Capacitance
C
oss
Output Capacitance
Effective Output Capacitance
C
oss eff.
Diode Characteristics
Parameter
Continuous Source Current
I
S
(Body Diode)
Pulsed Source Current
I
SM
(Body Diode)
V
SD
Diode Forward Voltage
t
rr
Reverse Recovery Time
Q
rr
Reverse Recovery Charge
t
on
Forward Turn-On Time
Typ. Max. Units
–––
–––
–––
62
110
61
240
1.3
93
170
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
Notes:
Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11)
Limited by T
Jmax ,
starting T
J
= 25°C, L = 0.45mH, R
G
= 25, I
AS
= 30A, V
GS
=10V. Part not recommended for use above this value.
SD
30A,
di/dt
280A/µs,
V
DD
V
(BR)DSS
, T
J
175°C.
I
Pulse width
1.0ms;
duty cycle
2%.
oss
eff. is a fixed capacitance that gives the same charging time as C
oss
while V
DS
is rising from 0 to 80% V
DSS
C
Limited by T
Jmax
, see Fig.12a, 12b, 15, 16 for typical repetitive avalanche performance.
This value determined from sample failure population, starting T
J
= 25°C, L = 0.45mH, R
G
= 25, I
AS
= 30A, V
GS
=10V.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to
application note #AN-994
is measured at T
J
approximately 90°C.
R
2
2015-12-14
AUIRLR3915
10000
1000
100
10
1
0.1
0.01
0.001
0.1
1
10
100
1000
BOTTOM
TOP
VGS
15V
10V
5.0V
3.0V
2.7V
2.5V
2.25V
2.0V
1000
TOP
VGS
15V
10V
5.0V
3.0V
2.7V
2.5V
2.25V
2.0V
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
100
BOTTOM
10
2.0V
1
2.0V
20µs PULSE WIDTH
Tj = 25°C
20µs PULSE WIDTH
Tj = 175°C
0.1
0.1
1
10
100
1000
VDS , Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig. 1
Typical Output Characteristics
Fig. 2
Typical Output Characteristics
1000.00
70
G fs , Forward Transconductance (S)
ID, Drain-to-Source Current
)
T J = 25°C
60
50
40
30
20
10
0
T J = 175°C
T J = 25°C
100.00
T J = 175°C
10.00
1.00
0.10
1.0
3.0
5.0
7.0
VDS = 25V
20µs PULSE WIDTH
9.0
11.0
13.0
15.0
0
10
20
30
40
50
60
VGS, Gate-to-Source Voltage (V)
ID,Drain-to-Source Current (A)
Fig. 3
Typical Transfer Characteristics
Fig. 4
Typical Forward Trans conductance
Vs. Drain Current
2015-12-14
3
AUIRLR3915
100000
VGS = 0V,
f = 1 MHZ
Ciss = C + C , C SHORTED
gs gd ds
Crss = C
gd
V
GS
, Gate-to-Source Voltage (V)
12
I
D
=
30A
10
10000
Coss = C + C
ds gd
V
DS
= 44V
V
DS
= 27V
V
DS
= 11V
C, Capacitance(pF)
8
Ciss
1000
6
Coss
100
4
Crss
2
10
1
10
100
0
0
10
20
30
40
50
60
70
VDS, Drain-to-Source Voltage (V)
Q
G
, Total Gate Charge (nC)
Fig 5.
Typical Capacitance vs.
Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs.
Gate-to-Source Voltage
1000
1000
OPERATION IN THIS AREA
LIMITED BY R DS (on)
100
10
T = 175
J
°
C
ID, Drain-to-Source Current (A)
I
SD
, Reverse Drain Current (A)
100
100µsec
10
Tc = 25°C
Tj = 175°C
Single Pulse
1
1
10
T = 25
°
C
J
1
1msec
0.1
0.0
0.5
1.0
V
GS
= 0 V
1.5
2.0
10msec
100
1000
V
SD
,Source-to-Drain Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig. 7
Typical Source-to-Drain Diode
Forward Voltage
4
Fig 8.
Maximum Safe Operating Area
2015-12-14
AUIRLR3915
2.5
70
I
D
= 61A
LIMITED BY PACKAGE
60
2.0
50
R
DS(on)
, Drain-to-Source On Resistance
(Normalized)
I
D
, Drain Current (A)
1.5
40
30
1.0
20
0.5
10
0.0
-60
-40
-20
0
20
40
60
80
100
V
GS
= 10V
120
140
160
180
0
25
50
75
100
125
150
175
T
C
, Case Temperature
( °C)
T
J
, Junction Temperature
(
°
C)
Fig 9.
Maximum Drain Current Vs.
Case Temperature
Fig 10.
Normalized On-Resistance
Vs. Temperature
10
(Z
thJC
)
1
D = 0.50
Thermal Response
0.20
0.10
0.1
0.05
0.02
0.01
SINGLEPULSE
(THERMAL RESPONSE)
Notes:
1. Dutyfactor D =
2. PeakT
0.01
0.00001
0.0001
0.001
0.01
t
1
/ t
2
thJC
J
= P
DM
x Z
P
DM
t
1
t
2
+T
C
1
0.1
t
1
, Rectangular Pulse Duration (sec)
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
5
2015-12-14
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