voltage protection, and current limiting with independent
current sense on each phase. It is available in a 28-pin
TSSOP package.
Applications
•
•
•
•
•
Power supply for Pentium
®
IV
Power supply for Athlon
®
Power supply for Ultrasparc™
VRM for Pentium IV processor
Programmable step-down power supply
Block Diagram
+12V
VFB
FAN5094
+
PHASE
+12V
VFB
CLK
CLK
PHASE
ISHR
+
ISHR
+12V
Processor
FAN5094
+12V
VFB
Pentium is a registered trademark of Intel Corporation. Athlon is a registered trademark of AMD. Programmable Active Droop is a trademark of Fairchild Semiconductor.
REV. 1.0.2 5/13/02
FAN5094
PRODUCT SPECIFICATION
Pin Assignments
VID0
VID1
VID2
VID3
VID4
CLK
BYPASS
AGND
LDRVB
GNDB
ISNSB
SWB
HDRVB
BOOTB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VFB
RT
ENABLE/SS
DROOP/E*
ISHR
PHASE
PWRGD
VCC
LDRVA
GNDA
ISNSA
SWA
HDRVA
BOOTA
FAN5094
Pin Definitions
Pin Number
1-5
6
Pin Name
VID0-4
CLK
Pin Function Description
Voltage Identification Code Inputs.
These open collector/TTL compatible
inputs will program the output voltage over the ranges specified in Table 1.
Clock.
When PHASE is high, this pin puts out a clock signal synchronized
180
°
out of phase with the internal master clock. When PHASE is low, this pin
is an input for a synchronizing clock signal.
5V Rail.
Bypass this pin with a 0.1
µ
F ceramic capacitor to AGND.
Analog Ground.
Return path for low power analog circuitry. This pin should
be connected to a low impedance system ground plane to minimize ground
loops.
Low Side FET Driver for B.
Connect this pin to the gate of an N-channel
MOSFET for synchronous operation. The trace from this pin to the MOSFET
gate should be <0.5”.
Ground B.
Ground-side current sense pin. Connect directly to low-side
MOSFET source, or to sense resistor ground.
Current Sense B.
Sensor side of current sense. Attach to low-side MOSFET
drain, or to source side of sense resistor.
High side driver source and low side driver drain switching node B.
Gate
drive return for high side MOSFET, and negative input for low-side MOSFET
current sense.
High Side FET Driver B.
Connect this pin to the gate of an N-channel
MOSFET. The trace from this pin to the MOSFET gate should be <0.5”.
Bootstrap B.
Input supply for high-side MOSFET.
Bootstrap A.
Input supply for high-side MOSFET.
High Side FET Driver A.
Connect this pin to the gate of an N-channel
MOSFET. The trace from this pin to the MOSFET gate should be <0.5”.
High side driver source and low side driver drain switching node A.
Gate
drive return for high side MOSFET, and negative input for low-side MOSFET
current sense.
Current Sense A.
Sensor side of current sense. Attach to low-side MOSFET
drain, or to source side of sense resistor.
7
8
BYPASS
AGND
9
LDRVB
10
11
12
GNDB
ISNSB
SWB
13
14
15
16
17
HDRVB
BOOTB
BOOTA
HDRVA
SWA
18
ISNSA
2
REV. 1.0.2 5/13/02
PRODUCT SPECIFICATION
FAN5094
Pin Definitions
Pin Number
19
20
GNDA
(continued)
Pin Function Description
Ground A.
Ground-side current sense pin. Connect directly to low-side
MOSFET source, or to sense resistor ground.
Low Side FET Driver for A.
Connect this pin to the gate of an N-channel
MOSFET for synchronous operation. The trace from this pin to the MOSFET
gate should be <0.5”.
VCC.
Internal IC supply. Connect to system 12V supply, and decouple with a
0.1
µ
F ceramic capacitor.
Power Good Flag.
An open collector output that will be logic LOW if the
output voltage is not within +/-5% of the nominal output voltage setpoint.
Phase Control.
Connecting this pin to bypass causes a synchronized clock
signal to appear on CLK. Connecting this pin to ground allows the CLK pin to
accept a clock signal for synchronization.
Current Share.
Connecting this pin to the ISHR pin of another FAN5094
enables current sharing.
Droop Control/E*-mode Control.
A resistor from this pin to ground sets the
amount of droop by controlling the gain of the current sense amplifier.
Connecting this pin to bypass turns off Phase A.
Output Enable.
A logic LOW on this pin will disable the output. An internal
current source allows for open collector control. This pin also doubles as soft
start.
Frequency Set.
A resistor from this pin to ground sets the switching
frequency. See Apps section.
Voltage Feedback.
Connect to the desired regulation point at the output of
the converter.
Pin Name
LDRVA
21
22
23
VCC
PWRGD
PHASE
24
25
ISHR
DROOP/E*
26
ENABLE/SS
27
28
RT
VFB
Absolute Maximum Ratings
Parameter
Supply Voltage VCC
Supply Voltages BOOTA, BOOTB
Voltage Identification Code Inputs, VID0-VID4
VFB, ENABLE/SS, PWRGD, PHASE, CLK
SW, ISNS
PGNDA, PGNDB to AGND
Gate Drive Current, peak pulse
Junction Temperature, T
J
Storage Temperature
Lead Soldering Temperature, 10 seconds
Thermal Resistance Junction-to-case,
Θ
JA
-55
-65
300
16
-3
-0.5
3
150
150
Min.
Typ.
Max.
15
22
6
6
15
0.5
Units
V
V
V
V
V
V
A
°
C
°
C
°
C
°
C/W
REV. 1.0.2 5/13/02
3
FAN5094
PRODUCT SPECIFICATION
Recommended Operating Conditions
Parameter
Output Driver Supply, Boot
VCC
Input Logic HIGH
Input Logic LOW
Ambient Operating Temperature
0
Conditions
See Figure 1
Min.
16
10.8
2.0
0.8
70
12
Typ.
Max.
17
13.2
Units
V
V
V
V
°
C
Electrical Specifications
(V
CC
= 12V, V
OUT
= 1.500V, and T
A
= +25°C using circuit in Figure 1, unless otherwise noted.)
The
•
denotes specifications which apply over the full operating temperature range.
Parameter
Output Voltage
Output Current
Internal Reference Voltage
Initial Voltage Setpoint
Output Temperature Drift
Line Regulation
Droop
3
Programmable Droop Range
Total Output Variation, Steady
State
1
Total Output Variation,
Transient
2
Response Time
Gate Drive On-Resistance
Upper Drive Low Voltage
Upper Drive High Voltage
Lower Drive Low Voltage
Lower Drive High Voltage
Output Driver Rise & Fall Time
Current Mismatch
Output Overvoltage Detect
Efficiency
Oscillator Frequency
Oscillator Range
Maximum Duty Cycle
Minimum LDRV on-time
Input Low Current, VID pins
Soft Start Current
Enable Threshold
BYPASS Voltage
BYPASS Capacitor
4
ON
OFF
0.4
4.75
220
5
1000
5.25
V
nF
REV. 1.0.2 5/13/02
Conditions
See Table I
•
Min.
1.100
Typ.
60
Max.
1.850
Units
V
A
V
V
mV
µ
V
1.4925
I
LOAD
= 0.8A
T
A
= 0 to 70
°
C
V
IN
= 11.4V to 12.6V
I
LOAD
= 0.8A to I
max
R
DROOP
= TBD to TBD
I
LOAD
= 0.8A to I
max
I
LOAD
= 0.8A to I
max
∆
V
OUT
= 10mV
V
HDRV
– V
SW
at I
sink
= 10µA
V
BOOT
– V
HDRV
at I
source
= 10µA
I
sink
= 10µA
V
CC
– V
LDRV
at I
source
= 10µA
See Figure 2
R
DS,on
(A) = R
DS,on
(B)
•
I
LOAD
= I
max
,
I
LOAD
= 2A, E*-mode enabled
RT = 41.2K
Ω
RT = 125K
Ω
to 12.5K
Ω
RT = 125K
Ω
RT=12.5K
Ω
V
VID
= 0.4V
•
450
200
2.1
•
•
•
-90
-10
1.430
1.430
1.488
1.5000
1.500
+5
+130
-100
1.5075
1.512
-110
0
1.570
1.570
mV
%V
OUT
V
V
nsec
Ω
V
V
V
V
nsec
%
100
1.0
0.2
0.5
0.2
0.5
20
5
2.3
85
70
600
90
330
50
10
1.0
750
2000
V
%
KHz
KHz
%
nsec
µA
µA
V
PRODUCT SPECIFICATION
FAN5094
Electrical Specifications
(continued)
(V
CC
= 12V, V
OUT
= 1.500V, and T
A
= +25°C using circuit in Figure 1, unless otherwise noted.)
The
•
denotes specifications which apply over the full operating temperature range.
Parameter
PWRGD Threshold
PWRGD Hysteresis
PWRGD Output Voltage
PWRGD Delay
12V UVLO
UVLO Hysteresis
12V Supply Current
Over Temperature Shutdown
Over Temperature Hysteresis
HDRV and LDRV open
I
sink
= 4mA
High
→
Low
•
8.5
500
9.5
1.0
20
150
25
10.5
Conditions
Logic LOW, minimum
Logic LOW, maximum
•
•
Min.
85
108
Typ.
88
111
20
0.4
Max.
92
115
Units
%V
out
mV
V
µsec
V
V
mA
°C
°C
Notes:
1. Steady State Voltage Regulation includes Initial Voltage Setpoint, Output Ripple and Output Temperature Drift and is
measured at the converter’s VFB sense point.
2. As measured at the converter’s VFB sense point. For motherboard applications, the PCB layout should exhibit no more than
0.2m
Ω
trace resistance between the converter’s output capacitors and the CPU. Remote sensing should be used for optimal
performance.
3. Using the VFB pin for remote sensing of the converter’s output at the load, the converter will be in compliance with Intel’s
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