IDT74ALVCH16345
3.3V CMOS REGISTERED ADDRESS LINE DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS REGISTERED
ADDRESS LINE DRIVER
WITH 3-STATE OUTPUTS
AND BUS-HOLD
• 0.5 MICRON CMOS Technology
• Typical t
SK(o)
(Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• V
CC
= 3.3V ± 0.3V, Normal Range
• V
CC
= 2.7V to 3.6V, Extended Range
• V
CC
= 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
µ
• Rail-to-Rail output swing for increased noise margin
• Available in TSSOP package
IDT74ALVCH16345
FEATURES:
DESCRIPTION:
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
APPLICATIONS:
•
•
•
•
3.3V high speed systems
3.3V and lower voltage computing systems
High speed synchronous DRAM modules
PC motherboards
This registered address line driver is built using advanced dual metal CMOS
technology. The ALVCH16345 is configured with banks of four drivers, each
to be used in high speed synchronous memory applications.
The ALVCH16345 is ideal for driving memory modules in systems where
multiple memory modules are used. One each of the four output banks drives
a different module; modules can be added or removed without affecting the signal
integrity of the other modules in the system. Dual clock enables (CEx) allow use
of the device in high speed memory interleaving applications where the clock
can be alternately enabled and disabled, allowing the address to be held for
additional cycles during memory access.
The ALVCH16345 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining speed
performance.
The ALVCH16345 has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs and
eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
CE
1
OE
1
29
CE
2
56
CE
D
1
8
1
Q
1
CE
D
5
36
1
Q
5
D
4
Q
1
D
4
Q
5
CE
D
2
14
1
Q
2
CE
D
6
42
1
Q
6
D
4
Q
2
D
4
Q
6
CE
D
3
15
1
Q
3
CE
D
7
43
1
Q
7
D
4
Q
3
D
4
Q
7
CE
D
4
21
1
Q
4
CE
D
8
49
1
Q
8
D
4
Q
4
D
4
Q
8
CLK
28
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2004 Integrated Device Technology, Inc.
JANUARY 2004
DSC-4734/2
IDT74ALVCH16345
3.3V CMOS REGISTERED ADDRESS LINE DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max
V
TERM
(2)
Terminal Voltage with Respect to GND
–0.5 to +4.6
–0.5 to V
CC
+0.5
–65 to +150
–50 to +50
±50
–50
±100
V
TERM
(3)
Terminal Voltage with Respect to GND
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
I
> V
CC
Continuous Clamp Current, V
O
< 0
Continuous Current through each
V
CC
or GND
Unit
V
V
°C
mA
mA
mA
mA
CE
1
1
Q
1
2
Q
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CE
2
1
Q
8
2
Q
8
GND
3
Q
1
4
Q
1
GND
3
Q
8
4
Q
8
V
CC
D
1
1
Q
2
2
Q
2
V
CC
D
8
1
Q
7
2
Q
7
GND
3
Q
2
4
Q
2
GND
3
Q
7
4
Q
7
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
D
2
D
3
1
Q
3
2
Q
3
D
7
D
6
1
Q
6
2
Q
6
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output Capacitance
I/O Port Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
5
7
7
Max.
7
9
9
Unit
pF
pF
pF
GND
3
Q
3
4
Q
3
GND
3
Q
6
4
Q
6
NOTE:
1. As applicable to the device type.
D
4
V
CC
1
Q
4
2
Q
4
D
5
V
CC
1
Q
5
2
Q
5
GND
3
Q
4
4
Q
4
GND
3
Q
5
4
Q
5
FUNCTION TABLE
(1)
Inputs
CEx
H
X
L
L
X
CLK
X
L
↑
↑
X
OE
L
L
L
L
H
Dx
X
X
L
H
X
Output
xQx
B
2
B
2
L
H
Z
CLK
OE
TSSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
OE
Dx
xQx
CLK
CEx
Data Inputs
(1)
3-State Data Outputs
Clock Input
Clock Enable Inputs (Active LOW)
Description
3-State Output Enable Inputs (Active LOW)
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
↑
= LOW-to-HIGH Transition
2. Output level before the indicated steady-state input conditions were established.
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
2
IDT74ALVCH16345
3.3V CMOS REGISTERED ADDRESS LINE DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= –40°C to +85°C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input HIGH Current
Input LOW Current
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 2.3V, I
IN
= –18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
One input at V
CC
- 0.6V, other inputs at V
CC
or GND
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= V
CC
V
I
= GND
V
O
= V
CC
V
O
= GND
Test Conditions
Min.
1.7
2
—
—
—
—
—
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
—
—
–0.7
100
0.1
Max.
—
—
0.7
0.8
±5
±5
±10
±10
–1.2
—
40
V
mV
µA
µA
µA
µA
V
Unit
V
Quiescent Power Supply Current
Variation
—
—
750
µA
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol
I
BHH
I
BHL
I
BHH
I
BHL
I
BHHO
I
BHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
Parameter
(1)
Bus-Hold Input Sustain Current
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
V
CC
= 3V
V
CC
= 2.3V
V
CC
= 3.6V
Test Conditions
V
I
= 2V
V
I
= 0.8V
V
I
= 1.7V
V
I
= 0.7V
V
I
= 0 to 3.6V
Min.
– 75
75
– 45
45
—
Typ.
(2)
—
—
—
—
—
Max.
—
—
—
—
±500
Unit
µA
µA
µA
3
IDT74ALVCH16345
3.3V CMOS REGISTERED ADDRESS LINE DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
V
CC
= 3V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
I
OL
= 12mA
I
OL
= 24mA
Test Conditions
(1)
V
CC
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
2
1.7
2.2
2.4
2
—
—
—
—
—
Max.
—
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
V
Unit
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range.
T
A
= – 40°C to + 85°C.
OPERATING CHARACTERISTICS, T
A
= 25°C
V
CC
= 2.5V ± 0.2V
Symbol
C
PD
C
PD
Parameter
Power Dissipation Capacitance Outputs enabled
Power Dissipation Capacitance Outputs disabled
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
V
CC
= 3.3V ± 0.3V
Typical
Unit
pF
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.5V ± 0.2V
Symbol
f
MAX
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
SU
t
H
t
H
t
W
t
SK
(o)
t
SK
(b)
Propagation Delay
CLK to xQx
Output Enable Time
OE
to xQx
Output Disable Time
OE
to xQx
Set-up Time,
CEx
to CLK, HIGH or LOW
Set-up Time, Dx to CLK, HIGH or LOW
Hold Time,
CEx
to CLK, HIGH or LOW
Hold Time, Dx to CLK, HIGH or LOW
Pulse Width, CLK HIGH or LOW
Output Skew
(2)
Output Skew
(2)
1.5
1.5
0.5
0.5
3
—
—
—
—
—
—
—
—
—
1.5
1.5
0.5
0.5
3
—
—
—
—
—
—
—
—
—
1.5
1.5
0.5
0.5
3
—
—
—
—
—
—
—
500
350
ns
ns
ns
ns
ns
ps
ps
1.5
5.5
1.5
4.5
1.5
5.2
ns
1.5
5.2
1.5
5.1
1.5
4.5
ns
Parameter
Min.
150
1.5
Max.
—
5.4
V
CC
= 2.7V
Min.
150
1.5
Max.
—
4.4
V
CC
= 3.3V ± 0.3V
Min.
150
1.5
Max.
—
4
Unit
ns
ns
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. T
A
= – 40°C to + 85°C.
2 Skew between any two outputs of the same package and switching in the same direction. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs. For t
SK
(b) OUTPUT1
and OUTPUT2 are in the same bank.
4
IDT74ALVCH16345
3.3V CMOS REGISTERED ADDRESS LINE DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC(1)
= 3.3V±0.3V V
CC(1)
= 2.7V
6
2.7
1.5
300
300
50
6
2.7
1.5
300
300
50
V
CC(2)
= 2.5V±0.2V
2 x Vcc
Vcc
Vcc / 2
150
150
30
Unit
V
V
V
mV
mV
pF
SAME PHASE
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PHL
t
PHL
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
ALVC Link
Propagation Delay
ENABLE
CONTROL
INPUT
t
PZL
V
LOAD/2
OUTPUT
SWITCH
V
T
NORMALLY
CLOSED
LOW
t
PHZ
t
PZH
OUTPUT
SWITCH
NORMALLY
V
T
OPEN
HIGH
0V
t
PLZ
DISABLE
V
IH
V
T
0V
V
LOAD/2
V
LZ
V
OL
V
OH
V
HZ
0V
ALVC Link
V
CC
500Ω
Pulse
Generator
(1, 2)
V
LOAD
Open
GND
V
IN
D.U.T.
R
T
V
OUT
500Ω
C
L
ALVC Link
Test Circuit for All Outputs
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2ns; t
R
≤
2ns.
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other Tests
Switch
V
LOAD
GND
Open
t
SU
t
H
t
REM
t
SU
t
H
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
ALVC Link
INPUT
t
PLH1
t
PHL1
V
IH
V
T
0V
V
OH
V
T
V
OL
V
OH
V
T
V
OL
Set-up, Hold, and Release Times
OUTPUT 1
LOW-HIGH-LOW
PULSE
t
W
HIGH-LOW-HIGH
PULSE
V
T
t
SK
(x)
t
SK
(x)
OUTPUT 2
t
PLH2
t
PHL2
V
T
ALVC Link
Pulse Width
ALVC Link
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PHL2
-
t
PHL1
Output Skew - t
SK
(
X
)
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
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