1. Operation in excess of any parameter limit (except T
BS
) may cause permanent damage to the device.
2. MTTF >1 x 10
6
hours @ T
BS
<85°C. Operation in excess of maximum operating temperature (T
BS
) will degrade MTTF.
DC Specifications/Physical Properties
(T
A
= +25 °C, V
CC
- V
EE
= 5.0 volts, unless otherwise listed)
Symbol
V
CC
- V
EE
|I
CC
| or |I
EE
|
V
RFin(q)
V
RFout(q)
V
Logic
Parameters/Conditions
Operating bias supply difference
1
Bias supply current
Quiescent dc voltage appearing at all RF ports
Min
4.5
34
Typ
5.0
40
V
CC
Max
6.5
46
Units
volts
mA
volts
Nominal ECL Logic Level
(V
Logic
contact self-bias voltage, generated on-chip)
V
CC
-1.45
V
CC
-1.32
V
CC
-1.25
volts
Notes:
1. Prescaler will operate over full specified supply voltage range. V
CC
or V
EE
not to exceed limits specified in Absolute Maximum Ratings section.
2
RF Specifications
(T
A
= +25 °C, Z
0
= 50
W,
V
CC
- V
EE
= 5.0 volts)
Symbol
ƒ
in(max)
ƒ
in(min)
ƒ
Sel-Osc.
P
in
Parameters/Conditions
Maximum input frequency of operation
Minimum input frequency of operation
1
(P
in
= -10 dBm)
Output Self-Oscillation Frequency
2
@ dc, (Square-wave input)
@ ƒ
in
= 500 MHz, (Sine-wave input)
ƒ
in
= 1 to 8 GHz
ƒ
in
= 8 to 10 GHz
ƒ
in
= 10 to 12 GHz
Min
12
Typ
14
0.2
3.4
Max
Units
GHz
0.5
GHz
GHz
-15
-15
-15
-10
-5
>-25
>-20
>-20
>-15
>-10
15
30
-153
+10
+10
+10
+5
-1
dBm
dBm
dBm
dBm
dBm
dB
dB
dBc/Hz
RL
S
12
M
N
Jitter
Small-Signal Input/Output Return Loss (@ ƒ
in
<10 GHz)
Small-Signal Reverse Isolation (@ ƒ
in
<10 GHz)
SSB Phase noise (@ P
in
= 0 dBm, 100 KHz offset from a ƒ
ou
t =
1.2 GHz Carrier)
Input signal time variation @ zero-crossing (ƒ
in
= 10 GHz, P
in
=
-10 dBm)
Output transition time (10% to 90% rise/fall time)
@ ƒ
out
< 1 GHz
@ ƒ
out
= 2.5 GHz
@ ƒ
out
= 3.0 GHz
-2.0
-3.5
-4.5
1
ps
T
r
or T
f
P
out3
70
0.0
-1.5
-2.5
0.5
0.42
0.37
-50
ps
dBm
dBm
dBm
volts
volts
volts
dBm
|V
out(p-p)
|
4
@ ƒ
out
< 1 GHz
@ ƒ
out
= 2.5 GHz
@ ƒ
out
= 3.0 GHz
P
Spitback
ƒ
out
power level appearing at RF
in
or RF
out
(@ ƒ
in
10 GHz,
Unused RF
out
or RF
out
unterminated)
ƒ
out
power level appearing at RF
in
or RF
out
(@ ƒ
in
10 GHz, Both
RF
out
or RF
out
unterminated)
-55
dBm
P
feedthru
H
2
Power level of ƒ
in
appearing at RF
out
or RF
out
(@ ƒ
in
= 12 GHz,
Pin = 0 dBm, Referred to P
in
(ƒ
in
))
Second harmonic distortion output level (@ ƒ
out
= 3.0 GHz,
Referred to P
out
(ƒ
out
))
-30
dBc
-25
dBc
Notes:
1. For sine–wave input signal. Prescaler will operate down to dc for square–wave input signal. Min. divide frequency limited by input slew rate.
2. Prescaler can exhibit this output signal under bias in the absence of an RF input signal. This condition can be eliminated by use of the Input dc offset
technique described on page 4.
3. Fundamental of output square wave’s Fourier Series.
4. Square wave amplitude calculated from P
out
.
3
Applications
The HMMC-3124 is designed for
use in high frequency
communications, microwave
instrumentation, and EW radar
systems where low phase–noise
PLL control circuitry or broad–
band frequency translation is
required.
Operation
The device is designed to
operate when driven with either
a single–ended or differential
sinusoidal input signal over a
200 MHz to 12 GHz bandwidth.
Below 200 MHz the prescaler
input is “slew–rate” limited,
requiring fast rising and falling
edge speeds to properly divide.
The device will operate at
frequencies down to dc when
driven with a square–wave.
Due to the presence of an off–
chip RF–bypass capacitor inside
the package (connected to the
V
CC
contact on the device), and
the unique design of the device
itself, the component may be
biased from either a single
positive or single negative
supply bias. The backside of the
package is not dc connected to
any dc bias point on the device.
For positive supply operation,
V
CC
pins are nominally biased at
any voltage in the +4.5 to +6.5
volt range with pin 8 (V
EE
)
grounded. For negative bias
operation V
CC
pins are typically
grounded and a negative voltage
between - 4.5 to - 6.5 volts is
applied to pin 8 (V
EE
).
ac–Coupling and dc–Blocking
All RF ports are dc connected
on–chip to the V
CC
contact
through on–chip 50W resistors.
Under any bias conditions where
V
C C
is not dc grounded the RF
ports should be ac coupled via
series capacitors mounted on
the PC– board at each RF port.
Only under bias conditions
where V
CC
is dc grounded (as is
typical for negative bias supply
operation) may the RF ports be
direct coupled to adjacent
circuitry or in some cases, such
as level shifting to subsequent
stages. In the latter case the
package heat sink may be
“floated” and bias applied as the
difference between V
CC
and V
EE
.
Input dc Offset
If an RF signal with sufficient
signal to noise ratio is present at
the RF input lead, the prescaler
will operate and provide a
divided output equal the input
frequency divided by the divide
modulus. Under certain “ideal”
conditions where the input is
well matched at the right input
frequency, the component may
“self–oscillate”, especially under
small signal input powers or
with only noise present at the
input. This “self–oscillation” will
produce an undesired output
signal also known as a false
trigger. To prevent false triggers
or self– oscillation conditions,
apply a 20 to 100 mV dc offset
voltage between the RFi n and
RFi n ports. This prevents noise
or spurious low level signals
from triggering the divider.
Adding a 10KW resistor between
the unused RF input to a contact
point at the VEE potential will
result in an offset of » 25mV
between the RF inputs. Note,
however, that the input
sensitivity will be reduced
slightly due to the presence of
this offset.
V
CC
6
V
CC
4
V
CC
2
150p
Vcc
By
poss
Vcc
Vcc
50
50
OUT
50
50
IN
IN
5
7
IN
÷
IN
Vee
Vpwr
sel
3
OUT
OUT
OUT
Pin 1
SOIC8 w/Backside GND
8
V
EE
Figure 1. Simplified Schematic
4
Assembly Notes
Independent of the bias applied
to the package, the backside of
the package should always be
connected to both a good RF
ground plane and a good
thermal heat sinking region on
the PC–board to optimize
performance. For single–ended
output operation the unused RF
output lead should be
terminated into 50W to a contact
point at the V
CC
potential or to
RF ground through a dc blocking
capacitor.
A minimum RF and thermal PC
board contact area equal to or
greater than 2.67 x 1.65 mm
(0.105" x 0.065") with eight
0.020" diameter plated–wall
thermal vias is recommended.
MMIC ESD precautions,
handling considerations, die
attach and bonding methods are
critical factors in successful
GaAs MMIC performance and
reliability.
Agilent application note #54,
“GaAs MMIC ESD, Die Attach
and Bonding Guidelines”
provides basic information on
these subjects.
Moisture Sensitivity
Classification: Class 1, per
JESD22-A112-A.
Additional References:
PN #18, “HBT Prescaler
Evaluation Board.”
Notes:
- All dimensions in millimeters.
- Refer to JEDEC Outline MS-012 for
additional tolerances.
Symbol
A
A1
B
C
D
E
e
H
L
a
Figure 2. Package & Dimensions
-
Min
1.35
0.0
0.33
0.19
4.80
3.80
Max
1.75
.25
0.51
.025
5.00
4.00
1.27 BSC
5.80
0.40
0°
6.20
1.27
8°
VCC (+4 .5 to +6 .5 vo lts)
-
Exposed heat slug area on pkg bottom =
2.67 x 1.65
Exposed heat sink on package bottom must
be soldered to PCB RF ground plane.
~ 1 mf Mon o b lo ck
C apacito r
To operate component from a negative supply, ground each
VCCconnection and supply VEE witha negative voltage (-4.5
to -6.5v) bypassed to ground with~1 m capacitor.
f
HMM
C-3124
9618
RFin
VCC
RFin
VEE
VCC
RFout
VCC
RFout
RFout should be terminated in 50Ω to ground. (dc blocking
capacitor required for positive bias configuration.)
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