STK12C68, STK12C68-5 (SMD5962-94599)
8Kx8 AutoStore nvSRAM
FEATURES
• 25, 35, 45, 55 ns Read Access & Write Cycle Time
• Unlimited Read/Write Endurance
• Automatic Non-volatile STORE on Power Loss
• Non-Volatile STORE Under Hardware or Software
Control
• Automatic RECALL to SRAM on Power Up
• Unlimited RECALL Cycles
• 1 Million STORE Cycles
• 100-Year Non-volatile Data Retention
• Single 5V ± 10% Power Supply
• Commercial, Industrial, Military Temperatures
• 28-pin 330-mil SOIC, 300-mil PDIP, and 600-mil
PDIP Packages (RoHS-Compliant)
• 28-Pin CDIP and LCC Military Packages
DESCRIPTION
The Simtek STK12C68 is a 64Kb fast static RAM
with a non-volatile Quantum Trap storage element
included with each memory cell.
The SRAM provides the fast access & cycle times,
ease of use and unlimited read & write endurance of
a normal SRAM.
Data transfers automatically to the non-volatile stor-
age cells when power loss is detected (the
STORE
operation). On power up, data is automatically
restored to the SRAM (the
RECALL
operation). Both
STORE and RECALL operations are also available
under software control.
The Simtek nvSRAM is the first monolithic non-vola-
tile memory to offer unlimited writes and reads. It is
the highest performance, most reliable non-volatile
memory available.
Block Diagram
V
cc
V
CAP
QUANTUM TRAP
128 x 512
ROW DECODER
A
5
A
6
A
7
A
8
A
9
A
11
A
12
STORE
STATIC RAM
ARRAY
128 X 512
RECALL
POWER
CONTROL
STORE/
RECALL
CONTROL
SOFTWARE
DETECT
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
INPUT BUFFERS
COLUMN I/O
COLUMN DEC
A
0
– A
12
A
0
A
1
A
2
A
3
A
4
A
10
G
E
W
This product conforms to specifications per the
terms of Simtek standard warranty. The product
has completed Simtek internal qualification testing
and has reached production status.
1
Document Control #ML0008 Rev 2.0
June, 2008
STK12C68, STK12C68-5 (SMD5962-94599)
Packages
V
Cap
A
7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
(T O P )
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
W
HSB
A
8
A
9
A
11
G
A
10
E
DQ
DQ
DQ
DQ
DQ
7
6
5
4
3
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
(TOP)
W
HSB
A
8
A
9
A
11
G
A
10
E
DQ
7
DQ
6
DQ
5
V
CAP
DQ
2
A
12
DQ
3
28-pin SOIC
28-pin DIP
28-pin LCC
Pin Descriptions
Pin Name
A
12
-A
0
DQ
7
-DQ
0
E
W
G
V
CC
HSB
Input
I/O
Input
Input
Input
Power Supply
I/O
I/O
Description
Address: The 13 address inputs select one of 8,192 bytes in the nvSRAM array
Data: Bi-directional 8-bit data bus for accessing the nvSRAM
Chip Enable: The active low E input selects the device
Write Enable: The active low W enables data on the DQ pins to be written to the address
location latched by the falling edge of E
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
Power: 5.0V, +10%
Hardware Store Busy: When low this output indicates a Store is in progress. When pulled
low external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor
keeps this pin high if not connected. (Connection Optional).
AutoStore Capacitor: Supplies power to nvSRAM during power loss to store data from
SRAM to nonvolatile storage elements.
Ground
V
CAP
V
SS
Power Supply
Power Supply
Document Control #ML0008 Rev 2.0
June, 2008
2
DQ
4
V
SS
V
CC
STK12C68, STK12C68-5 (SMD5962-94599)
ABSOLUTE MAXIMUM RATINGS
a
Voltage on Input Relative to Ground . . . . . . . . . . . . . –0.5V to 7.0V
Voltage on Input Relative to V
SS
. . . . . . . . . . –0.6V to (V
CC
+ 0.5V)
Voltage on DQ
0-7
or HSB . . . . . . . . . . . . . . . . –0.5V to (V
CC
+ 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . .–55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . .15mA
Package Thermal Characteristics - See Website at http://www.simtek.com
Note a: Stresses greater than those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
DC CHARACTERISTICS
COMMERCIAL
SYMBOL
I
CC1b
PARAMETER
MIN
Average V
CC
Current
MAX
85
75
65
--
3
10
2
27
24
20
--
1.5
±1
±5
2.2
V
SS
– .5
2.4
0.4
0.4
0
70
–40/-55
V
CC
+ .5
0.8
2.2
V
SS
– .5
2.4
0.4
0.4
85/125
INDUSTRIAL
MILITARY
MIN
MAX
85
75
65
55
3
10
2
27
24
20
19
2.5
±1
±5
V
CC
+ .5
0.8
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
μA
μA
V
V
V
V
V
°C
UNITS
(VCC = 5.0V
±
10%)
e
NOTES
t
AVAV
= 25ns (commercial and industrial only)
t
AVAV
= 35ns
t
AVAV
= 45ns (commercial and industrial only)
t
AVAV
= 55ns
All Inputs Don’t Care, V
CC
= max
W
≥
(V
CC
– 0.2V)
All Others Cycling, CMOS Levels
All Inputs Don’t Care
t
AVAV
= 25ns, E
≥
V
IH
(commercial and industrial only)
t
AVAV
= 35ns, E
≥
V
IH
t
AVAV
= 45ns, E
≥
V
IH
(commercial and industrial only)
t
AVAV
= 55ns, E
≥
V
IH
E
≥
(V
CC
– 0.2V)
All Others V
IN
≤
0.2V or
≥
(V
CC
– 0.2V)
V
CC
= max
V
IN
= V
SS
to V
CC
V
CC
= max
V
IN
= V
SS
to V
CC
, E or G
≥
V
IH
All Inputs
All Inputs
I
OUT
= – 4mA except HSB
I
OUT
= 8mA except HSB
I
OUT
= 3mA
I
CC2c
I
CC3
b
Average V
CC
Current during
STORE
Average V
CC
Current at t
AVAV
= 200ns
5V, 25°C, Typical
Average V
CAP
Current during AutoStore
Cycle
Average V
CC
Current
(Standby, Cycling TTL Input Levels)
I
CC4c
I
SB1d
I
SB2d
I
ILK
I
OLK
V
IH
V
IL
V
OH
V
OL
V
BL
T
A
V
CC
Standby Current
(Standby, Stable CMOS Input Levels)
Input Leakage Current
Off-State Output Leakage Current
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Logic “0” Voltage on HSB Output
Operating Temperature
Note b:
Note c:
Note d:
Note e:
I
CC1
and I
CC3
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
I
CC2
and I
CC4
are the average currents required for the duration of the respective
STORE
cycles (t
STORE
) .
E
≥
V
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out.
V
CC
reference levels throughout this datasheet refer to V
CC
if that is where the power supply connection is made, or V
CAP
if V
CC
is connected to ground.
AC TEST CONDITIONS
Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 3V
Input Rise and Fall Times
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤
5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
5.0V
480 Ohms
OUTPUT
255 Ohms
30 pF
INCLUDING
SCOPE AND
FIXTURE
CAPACITANCE
f
SYMBOL
C
IN
C
OUT
PARAMETER
Input Capacitance
Output Capacitance
(T
A
= 25°C, f = 1.0MHz)
MAX
8
7
UNITS
pF
pF
CONDITIONS
ΔV
= 0 to 3V
ΔV
= 0 to 3V
Note f:
These parameters are guaranteed but not tested.
Figure 1. AC Output Loading
Document Control #ML0008 Rev 2.0
June, 2008
3
STK12C68, STK12C68-5 (SMD5962-94599)
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
#1, #2
1
2
3
4
5
6
7
8
9
10
11
t
ELQV
t
AVAVg,
t
ELEHg
t
AVQVh
t
GLQV
t
AXQXh
t
ELQX
Alt.
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Address Change or Chip Enable to
Output Active
Address Change or
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
0
25
0
10
0
35
5
5
10
0
10
0
45
25
25
10
5
5
10
0
12
0
55
PARAMETER
STK12C68,
STK12C68-5-25
MIN
MAX
25
35
35
15
5
5
12
0
12
STK12C68,
STK12C68-5-35
MIN
MAX
35
45
45
20
5
5
12
(V
CC
= 5.0V
±
10%)
e
STK12C68,
STK12C68-5-45
MIN
MAX
45
55
55
35
STK12C68,
STK12C68-5-55
MIN
MAX
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNITS
t
EHQZi
t
GLQX
t
GHQZi
t
ELICCH
f
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
t
EHICCLf
Note g: W and HSB must be high during SRAM READ cycles.
Note h: Device is continuously selected with E and G both low.
Note i: Measured
±
200mV from steady state output voltage.
SRAM READ CYCLE #1:
Address Controlled
g
,
h
2
t
AVAV
ADDRESS
5
t
AXQX
DQ (DATA OUT)
DATA VALID
3
t
AVQV
SRAM READ CYCLE #2:
E and G Controlled
g
t
AVAV
ADDRESS
t
ELQV
E
27
1
2
t
ELQX
t
EHQZ
7
6
t
EHICCL
11
t
AVEL
G
t
GLQV
4
t
GHQZ
9
t
GLQX
DQ (DATA OUT)
10
t
ELICCH
DATA VALID
8
ACTIVE
I
CC
STANDBY
Document Control #ML0008 Rev 2.0
June, 2008
4
STK12C68, STK12C68-5 (SMD5962-94599)
SRAM WRITE CYCLES #1 & #2
SYMBOLS
NO.
#1
12
13
14
15
16
17
18
19
20
21
t
AVAV
t
WLWH
t
ELWH
t
DVWH
t
WHDX
t
AVWH
t
AVWL
t
WHAX
t
WLQZ
i, j
(V
CC
= 5.0V
±
10%)
e
STK12C68,
STK12C68,
STK12C68,
STK12C68,
STK12C68-5-25 STK12C68-5-35 STK12C68-5-45 STK12C68-5-55 UNITS
MIN
MAX
MIN
35
25
25
12
0
25
0
0
10
5
5
13
5
MAX
MIN
45
30
30
15
0
30
0
0
14
5
MAX
MIN
55
45
45
25
0
45
0
0
15
MAX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PARAMETER
#2
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
Alt.
t
WC
t
WP
t
CW
t
DW
t
DH
t
AW
t
AS
t
WR
t
WZ
t
OW
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
25
20
20
10
0
20
0
0
t
WHQX
Note j:
Note k:
Note l:
If W is low when E goes low, the outputs remain in the high-impedance state.
E or W must be
≥
V
IH
during address transitions.
HSB must be high during SRAM WRITE cycles.
SRAM WRITE CYCLE #1:
W Controlled
k, l
12
t
AVAV
ADDRESS
14
t
ELWH
E
17
t
AVWH
13
t
WLWH
15
t
DVWH
DATA IN
20
t
WLQZ
DATA OUT
PREVIOUS DATA
HIGH IMPEDANCE
DATA VALID
19
t
WHAX
18
t
AVWL
W
16
t
WHDX
21
t
WHQX
SRAM WRITE CYCLE #2:
E Controlled
k, l
12
t
AVAV
ADDRESS
18
t
AVEL
E
14
t
ELEH
19
t
EHAX
17
t
AVEH
W
13
t
WLEH
15
t
DVEH
16
t
EHDX
DATA VALID
HIGH IMPEDANCE
DATA IN
DATA OUT
Document Control #ML0008 Rev 2.0
June, 2008
5
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