CY2287
100-MHz Spread Spectrum Clock Synthesizer/Driver with
USB, Hublink, and SDRAM Support
Features
• Mixed 2.5V and 3.3V Operation
• Multiple output clocks at different frequencies
— Three CPU clocks at 2.5V, up to 100 MHz
— Nine 3.3V SDRAM clocks at 100 MHz
— Eight synchronous PCI clocks at 33 MHz
— Two synchronous APIC clocks at 16.67 MHz or 33
MHz
— Two 3V66 clocks at 66 MHz
— Two USB clocks at 48 MHz
— One reference clock at 14.318 MHz
• Spread Spectrum clocking
— 31 kHz modulation frequency
— EPROM programmable percentage of spreading
— Default is –0.6%, which is recommended by Intel®
— Additional options of –0.25% and –0.4% available
• Power-down features
• I
2
C™ Interface
• Low skew and low jitter outputs
• Test Mode
• 56-pin SSOP package
Benefits
Usable with Pentium II, K6, and 6x86 Processors
Single-chip main motherboard clock generator
— High-Speed Processor Support
— Supports Two 4-Clock SDRAM DIMMs
— Support for Six PCI Slots
— Synchronous to the CPU Clock
— Hublink Support
— Universal Serial Bus Support
— Also used as an input strap to determine APIC frequency
Enables reduction of EMI
Supports mobile systems
Dynamic output control
Meets tight system timing requirements at high frequency
Enables ATE and “bed of nails” testing
Widely available, standard package enables lower cost
SSOP
Top View
REF0/SEL33 (14.318 MHz)
REF0/SEL33
V
DDREF
XTAL_IN
XTAL_OUT
V
SSREF
V
SS3V66
3V66_0
3V66_1
1
2
3
4
5
6
7
8
9
10
11
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
V
SSAPIC
APIC0
APIC1
V
DDAPIC
CPU0
V
DDCPU
CPU1
CPU2
V
SSCPU
V
SSSDRAM
SDRAM0
SDRAM1
V
DDSDRAM
SDRAM2
SDRAM3
V
SSSDRAM
SDRAM4
SDRAM5
V
DDSDRAM
SDRAM6
SDRAM7
V
SSSDRAM
SDRAM8
V
DDSDRAM
PWRDWN
SCLK
SDATA
SEL1
Logic Block Diagram
CPU [0–2] (66/100 MHz)
XTALIN
XTALOUT
14.318
MHz
OSC.
CPU
PLL
EPROM
Configurable
Logic
SDRAM [0-8] (100 MHz)
V
DD3V66
V
DDPCI
PCI0
PCI1
SEL0
SEL1
EPROM
PCI [0–7] (33MHz)
APIC [0–1] (16.67/33MHz)
3V66 [0–1] (66MHz)
SYS
PLL
PCI2
V
SSPCI
PCI3
PCI4
V
SSPCI
PCI5
PCI6
PCI7
V
DDPCI
AV
DD
AV
SS
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PWR_DWN
USB [0–1] (48MHz)
SCLK
SDATA
SERIAL INTERFACE
CONTROL LOGIC
V
SSUSB
USB0
USB1
V
DDUSB
SEL0
Intel and Pentium are registered trademarks of Intel Corporation.
I
2
C is a trademark of Philips Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
CY2287
•
12
13
408-943-2600
June 23, 1999
CY2287
Pin Summary
Name
REF/SEL33
Pins
1
Description
3.3V 14.31818-MHz clock output and power-on external select strap op-
tion for APIC clock frequency.
Strap LOW: APIC = PCI/2
Strap HIGH: APIC = 33.3 MHz
14.31818-MHz crystal input
14.31818-MHz crystal output
3.3V PCI clock outputs
3.3V Fixed 66.67-MHz clock outputs
3.3V Fixed 48-MHz clock outputs
3.3V LVTTL compatible inputs for logic selection
3.3V LVTTL compatible input. Device enters powerdown mode when held
LOW
2.5V 66.67-MHz or 100-MHz (selectable) host bus clock output
2.5V APIC clock outputs running synchronous with PCI clock frequency.
Selectable 16.67 MHz or 33.3 MHz
I
2
C compatible SDATA input
I
2
C compatible SCLK input
3.3V Power supply for REF output
REF ground
3V66 Ground
3.3V Power supply for 3V66 outputs
3.3V Power supply for PCI outputs
PCI ground
3.3V Analog power supply
Analog ground
USB ground
3.3V Power supply for USB outputs
3.3V Power supply for SDRAM outputs
SDRAM ground
CPU ground
2.5V Power supply for CPU outputs
2.5V Power supply for APIC outputs
APIC ground
XTAL_IN
[1]
XTAL_OUT
[1]
PCI [0–7]
3V66 [0–1]
USB [0–1]
SEL [0–1]
PWRDWN
CPU [0–2]
SDRAM [0–8]
APIC [0–1]
SDATA
SCLK
V
DDREF
V
SSREF
V
SS3V66
V
DD3V66
V
DDPCI
V
SSPCI
AV
DD
AV
SS
V
SSUSB
V
DDUSB
V
DDSDRAM
V
SSSDRAM
V
SSCPU
V
DDCPU
V
DDAPIC
V
SSAPIC
3
4
11, 12, 13, 15, 16, 18, 19, 20
7, 8
25, 26
28, 29
32
49, 50, 52
54, 55
30
31
2
5
6
9
10, 21
14, 17
22
23
24
27
33, 38, 44
35, 41, 47
48
51
53
56
35, 36, 37, 39, 40, 42, 43, 45, 46 3.3V SDRAM clock outputs running 100 MHz
Note:
1. For best accuracy, use a parallel-resonant crystal, C
LOAD
= 18 pF. For crystals with different C
LOAD
, please refer to the application note, “Crystal Oscillator
Topics.”
2
CY2287
Function Table
SEL2
0
0
0
0
1
1
1
1
[2]
SEL1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
CPU
(MHz)
Hi-Z
TCLK /2
66.67
100
66.67
100
66.67
100
[3]
SDRAM
(MHz)
Hi-Z
TCLK/2
100
100
100
100
100
100
SEL2
[2]
0
0
X
0
0
1
1
1
1
3V66
(MHz)
Hi-Z
TCLK/3
66.67
66.67
66.67
66.67
66.67
66.67
SEL1
0
0
X
1
1
0
0
1
1
PCI
(MHz)
Hi-Z
TCLK/8
33.33
33.33
33.33
33.33
33.33
33.33
USB
(MHz)
Hi-Z
TCLK/2
48
48
48
48
48
48
SEL0
0
1
X
0
1
0
1
0
1
REF
(MHz)
Hi-Z
TCLK
14.318
14.318
14.318
14.318
14.318
14.318
APIC
[4]
(MHz)
Hi-Z
TCLK/16
16.67
16.67
16.67
16.67
16.67
16.67
APIC
[5]
(MHz)
Hi-Z
TCLK/8
33.33
33.33
33.33
33.33
33.33
33.33
Spread Spectrum
[2]
X
X
0
1
1
1
1
1
1
Spread Spectrum Margin
N/A
N/A
N/A
–0.6%
–0.6%
–0.25%
–0.25%
–0.4%
–0.4%
Actual Clock Frequency Values
Clock Output
CPUCLK
CPUCLK
USBCLK
Notes:
2.
3.
4.
5.
Not a dedicated input pin. This selection must be addressed via I
2
C interface.
TCLK supplied on the XTALIN pin in Test Mode.
SEL33 = LOW (power-on latch input).
SEL33 = HIGH (power-on latch input).
Target
Frequency (MHz)
66.67
100.0
48.0
Actual
Frequency (MHz)
66.288
99.432
48.008
PPM
–5230
–5680
+167
3
CY2287
Serial Configuration Map
• The Serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
.
.
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
• Reserved and unused bits must be programmed to “0”.
• I
2
C Address for the CY2287 is:
Byte 2: PCI Control Register
(1 = Enable, 0 = Disable)
Default = Enable (for Bit [1:7])
Default = Disable (for Bit 0)
Bit
Pin #
PCI7
PCI6
PCI5
PCI4
PCI3
PCI2
PCI1
Reserved
Description
Bit 7 20
Bit 6 19
Bit 5 18
Bit 4 16
Bit 3 15
Bit 2 13
Bit 1 12
Bit 0 11
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
0
Byte 0: Spread Spectrum, USB, SDRAM8
Control Register
(1 = Enable, 0 = Disable)
Default = Enable (for Bit [0:2])
Default = Disable (for Bit [3:7])
Bit
Pin #
Reserved
Reserved
Reserved
SEL2
Spread Spectrum (Default = Disable)
USB1
USB0
CPU2
Description
Bit 7 --
Bit 6 --
Bit 5 --
Bit4
Bit3
Bit2
Bit1
Bit0
--
--
26
25
49
Byte 3: Peripheral Control Register
(0 = Enable, 1 = Disable)
Default = Enable
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
8
7
11
34
54
55
50
52
Pin #
3V66_1
3V66_0
PCI0
SDRAM8
APIC1
APIC0
CPU1
CPU0
Description
Byte 1: SDRAM Control Register
(1 = Enable, 0 = Disable)
Default = Enable
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
36
37
39
40
42
43
45
46
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Description
Byte 4: Reserved Register
(0 = Enable, 1 = Disable)
Default = Disable
Bit
Pin #
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Bit 7 --
Bit 6 --
Bit 5 --
Bit 4 --
Bit 3 --
Bit 2 --
Bit 1 --
Bit 0 --
4
CY2287
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Supply Voltage ..................................................–0.5 to +7.0V
Input Voltage .............................................. –0.5V to V
DD
+0.5
Storage Temperature (Non-Condensing) ... –65°C to +150°C
Max. Soldering Temperature (10 sec) ...................... +260°C
Junction Temperature ............................................... +150°C
Package Power Dissipation .............................................. 1W
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ............................. >2000V
Operating Conditions
Over Which Electrical Parameters are Guaranteed
Parameter
V
DD3.3V
V
DD2.5V
T
A
C
L
Description
3.3V Supply Voltages
2.5V Supply Voltages
Operating Temperature, Ambient
Max. Capacitive Load on
CPU, USB, REF, APIC
SDRAM, PCI, 3V66
Reference Frequency, Oscillator Nominal Value
14.318
Min.
3.135
2.375
0
Max.
3.465
2.625
70
20
30
14.318
MHz
Unit
V
V
°C
pF
f
(REF)
Electrical Characteristics
Over the Operating Range
Parameter
V
IH
V
IL
I
IH
I
IL
I
OH
Description
High-level Input Voltage
Low-level Input Voltage
Input High Current
Input Low Current
High-level Output Current
SCLK/SDATA
All inputs except SCLK/SDATA and crystal inputs
SCLK/SDATA
0 < V
IN
< V
DD
0 < V
IN
< V
DD
CPU
USB, REF
SDRAM
PCI, 3V66
APIC
I
OL
Low-level Output Current
CPU
USB, REF
SDRAM
PCI, 3V66
APIC
I
OZ
I
DD2
I
DD3
I
DDPD2
I
DDPD3
Output Leakage Current
2.5V Power Supply Current
3.3V Power Supply Current
2.5V Shutdown Current
3.3V Shutdown Current
Three-state
AV
DD
/V
DD33
= 3.465V, V
DD25
= 2.625V, F
CPU
= 100 MHz
AV
DD
/V
DD33
= 3.465V, V
DD25
= 2.625V, F
CPU
= 100 MHz
AV
DD
/V
DD33
= 3.465V, V
DD25
= 2.625V
[7]
AV
DD
/V
DDQ3
= 3.465V, V
DD25
= 2.625V
[7]
<1
<9
V
OH
= 2.0V
V
OH
= 2.4V
V
OH
= 2.4V
V
OH
= 2.4V
V
OH
= 2.0V
V
OL
= 0.4V
V
OL
= 0.4V
V
OL
= 0.4V
V
OL
= 0.4V
V
OL
= 0.4V
–10
–10
–16
–15
–30
–30
–16
19
10
20
20
19
[6]
Test Conditions
All inputs except SCLK/SDATA and crystal inputs
[6]
Min.
2.0
0.7
Typ
Max. Unit
V
V
DD
0.8
0.3
+10
+10
-60
–51
–100
–100
-60
49
24
49
49
49
10
100
280
500
500
µA
mA
mA
µA
µA
mA
V
V
DD
µA
µA
mA
Notes:
6. Crystal inputs have CMOS thresholds, nominally V
DD
/2.
7. Tested @ 500
µA.
Actual performance is much better. Call Cypress if tighter spec is required.
5
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