NB3L553
2.5 V / 3.3 V / 5.0 V
1:4 Clock Fanout Buffer
Description
The NB3L553 is a low skew 1−to 4 clock fanout buffer, designed for
clock distribution in mind. The NB3L553 specifically guarantees low
output−to−output skew. Optimal design, layout and processing
minimize skew within a device and from device to device.
Features
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MARKING DIAGRAMS*
8
8
1
SOIC−8
D SUFFIX
CASE 751
1
3L553
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
3L553
ALYW
G
•
•
•
•
•
•
•
•
•
•
Input/Output Clock Frequency up to 200 MHz
Low Skew Outputs (35 ps), Typical
RMS Phase Jitter (12 kHz – 20 MHz): 29 fs (Typical)
Output goes to Three−State Mode via OE
Operating Range: V
DD
= 2.375 V to 5.25 V
5 V Tolerant Input Clock I
CLK
Ideal for Networking Clocks
Packaged in 8−pin SOIC
Industrial Temperature Range
These are Pb−Free Devices
1
DFN8
MN SUFFIX
CASE 506AA
1
6P MG
G
Q1
Q2
I
CLK
Q3
Q4
*For additional marking information, refer to
Application Note AND8002/D.
6P = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
PINOUT DIAGRAM
OE
Figure 1. Block Diagram
V
DD
Q0
Q1
GND
1
2
3
4
8
7
6
5
OE
Q3
Q2
I
CLK
ORDERING INFORMATION
Device
NB3L553DG
NB3L553DR2G
NB3L553MNR4G
Package
SOIC−8
(Pb−Free)
SOIC−8
(Pb−Free)
DFN−8
(Pb−Free)
Shipping
†
98 Units/Rail
2500/Tape & Reel
1000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2017
1
January, 2017 − Rev. 9
Publication Order Number:
NB3L553/D
NB3L553
Table 1. OE, OUTPUT ENABLE FUNCTION
OE
0
1
Function
Disable
Enable
Table 2. PIN DESCRIPTION
Pin #
1
2
3
4
5
6
7
8
Name
V
DD
Q0
Q1
GND
I
CLK
Q2
Q3
OE
Type
Power
(LV)CMOS/(LV)TTL Output
(LV)CMOS/(LV)TTL Output
Power
(LV)CMOS Input
(LV)CMOS/(LV)TTL Output
(LV)CMOS/(LV)TTL Output
(LV)TTL Input
Description
Positive supply voltage (2.375 V to 5.25 V)
Clock Output 0
Clock Output 1
Negative supply voltage; Connect to ground, 0 V
Clock Input. 5.0 V tolerant
Clock Output 2
Clock Output 3
V
DD
for normal operation. Pin has no internal pullup or pull down resistor for open
condition default. Use from 1 to 10 kOhms external resistor to force an open con-
dition default state.
(DFN8 only) Thermal exposed pad must be connected to a sufficient thermal
conduit. Electrically connect to the most negative supply (GND) or leave uncon-
nected, floating open.
−
EP
Thermal Exposed Pad
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NB3L553
Table 3. MAXIMUM RATINGS
Symbol
V
DD
V
I
T
A
T
stg
q
JA
q
JC
q
JA
q
JC
Parameter
Positive Power Supply
Input Voltage
Operating Temperature Range,
Industrial
Storage Temperature Range
Thermal Resistance
(Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Thermal Resistance
(Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Condition 1
GND = 0 V
OE
I
CLK
−
−
0 lfpm
500 lfpm
(Note 1)
0 lfpm
500 lfpm
(Note 1)
Condition 2
−
GND = 0 V and
V
DD
= 2.375 V to 5.25 V
−
−
SOIC−8
SOIC−8
DFN8
DFN8
DFN8
Rating
6.0
GND – 0.5
v
V
I
v
V
DD
+ 0.5
GND – 0.5
v
V
I
v
5.75
≥
−40 to
≤
+85
−65 to +150
190
130
41 to 44
129
84
35 to 40
Unit
V
V
°C
°C
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
Table 4. ATTRIBUTES
Characteristic
ESD Protection
Human Body Model
Machine Model
Value
> 2 kV
> 150 V
Level 1
UL−94 code V−0 @ 0.125 in
531 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 2)
Flammability Rating
Transistor Count
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
Oxygen Index: 28 to 34
2. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
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NB3L553
Table 5. DC CHARACTERISTICS
(V
DD
= 2.375 V to 2.625 V, GND = 0 V, T
A
= −40°C to +85°C) (Note 3)
Symbol
I
DD
V
OH
V
OL
V
IH,
I
CLK
V
IL,
I
CLK
V
IH,
OE
V
IL,
OE
ZO
CIN
IOS
Characteristic
Power Supply Current @ 135 MHz, No Load
Output HIGH Voltage – I
OH
= −16 mA
Output LOW Voltage – I
OL
= 16 mA
Input HIGH Voltage, I
CLK
Input LOW Voltage, I
CLK
Input HIGH Voltage, OE
Input LOW Voltage, OE
Nominal Output Impedance
Input Capacitance, I
CLK
, OE
Short Circuit Current
Min
−
1.7
−
(V
DD
÷2)+0.5
−
1.8
−
−
−
−
Typ
25
−
−
−
−
−
−
20
5.0
±
28
Max
30
−
0.4
5.0
(V
DD
÷2)−0.5
V
DD
0.7
−
−
−
Unit
mA
V
V
V
V
V
V
W
pF
mA
DC CHARACTERISTICS
(V
DD
= 3.15 V to 3.45 V, GND = 0 V, T
A
= −40°C to +85°C) (Note 3)
Symbol
I
DD
V
OH
V
OL
V
OH
V
IH,
I
CLK
V
IL,
I
CLK
V
IH,
OE
V
IL,
OE
ZO
CIN
IOS
Characteristic
Power Supply Current @ 135 MHz, No Load
Output HIGH Voltage – I
OH
= −25 mA
Output LOW Voltage – I
OL
= 25 mA
Output HIGH Voltage – I
OH
= −12 mA (CMOS level)
Input HIGH Voltage, I
CLK
Input LOW Voltage, I
CLK
Input HIGH Voltage, OE
Input LOW Voltage, OE
Nominal Output Impedance
Input Capacitance, OE
Short Circuit Current
Min
−
2.4
−
V
DD
− 0.4
(V
DD
÷2)+0.7
−
2.0
0
−
−
−
Typ
35
−
−
−
−
−
−
−
20
5.0
±
50
Max
40
−
0.4
−
5.0
(V
DD
÷2)−0.7
V
DD
0.8
−
−
−
Unit
mA
V
V
V
V
V
V
V
W
pF
mA
DC CHARACTERISTICS
(V
DD
= 4.75 V to 5.25 V, GND = 0 V, T
A
= −40°C to +85°C) (Note 3)
Symbol
I
DD
V
OH
V
OL
V
OH
V
IH,
I
CLK
V
IL,
I
CLK
V
IH,
OE
V
IL,
OE
ZO
CIN
IOS
Characteristic
Power Supply Current @ 135 MHz, − No Load
Output HIGH Voltage – I
OH
= −35 mA
Output LOW Voltage – I
OL
= 35 mA
Output HIGH Voltage – I
OH
= −12 mA (CMOS level)
Input HIGH Voltage, I
CLK
Input LOW Voltage, I
CLK
Input HIGH Voltage, OE
Input LOW Voltage, OE
Nominal Output Impedance
Input Capacitance, OE
Short Circuit Current
Min
−
2.4
−
V
DD
− 0.4
(V
DD
÷2)
+ 1
−
2.0
−
−
−
−
Typ
45
−
−
−
−
−
−
−
20
5.0
±
80
Max
85
−
0.4
−
5.0
(V
DD
÷2)
− 1
V
DD
0.8
−
−
−
Unit
mA
V
V
V
V
V
V
V
W
pF
mA
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NB3L553
Table 6. AC CHARACTERISTICS; V
DD
= 2.5 V
+5%
(V
DD
= 2.375 V to 2.625 V, GND = 0 V, T
A
= −40°C to +85°C) (Note 3)
Symbol
f
in
t
r
/t
f
t
pd
t
skew
t
skew
Input Frequency
Output rise and fall times; 0.8 V to 2.0 V
Propagation Delay, CLK to Q
n
(Note 4)
Output−to−output skew; (Note 5)
Device−to−device skew, (Note 5)
Characteristic
Min
−
−
2.2
−
−
Typ
−
1.0
3.0
35
−
Max
200
1.5
5.0
50
500
Unit
MHz
ns
ns
ps
ps
AC CHARACTERISTICS; V
DD
= 3.3 V
+5%
(V
DD
= 3.15 V to 3.45 V, GND = 0 V, T
A
= −40°C to +85°C) (Note 3)
Symbol
f
in
t
jitter
(f)
t
r
/t
f
t
pd
t
skew
t
skew
Characteristic
Input Frequency
RMS Phase Jitter (Integrated 12 kHz −
20 MHz) (See Figures 2 and 3)
Output rise and fall times; 0.8 V to 2.0 V
Propagation Delay, CLK to Q
n
(Note 4)
Output−to−output skew; (Note 5)
Device−to−device skew, (Note 5)
f
carrier
= 100 MHz
Conditions
Min
−
−
−
2.0
−
−
Typ
−
18
0.6
2.4
35
−
Max
200
−
1.0
4.0
50
500
Unit
MHz
fs
ns
ns
ps
ps
AC CHARACTERISTICS; V
DD
= 5.0 V
+5%
(V
DD
= 4.75 V to 5.25 V, GND = 0 V, T
A
= −40°C to +85°C) (Note 3)
Symbol
f
in
t
jitter
(f)
t
r
/t
f
t
pd
t
skew
t
skew
Characteristic
Input Frequency
RMS Phase Jitter (Integrated 12 kHz −
20 MHz) (See Figures 2 and 3)
Output rise and fall times; 0.8 V to 2.0 V
Propagation Delay, CLK to Q
n
(Note 4)
Output−to−output skew; (Note 5)
Device−to−device skew, (Note 5)
f
carrier
= 100 MHz
Min
Min
−
−
−
1.7
−
−
Typ
−
29
0.3
2.5
35
−
Max
200
−
0.7
4.0
50
500
Unit
MHz
fs
ns
ns
ps
ps
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Outputs loaded with external R
L
= 33
W
series resistor and C
L
= 15 pF to GND. Duty cycle out = duty in. A 0.01
mF
decoupling capacitor should
be connected between V
DD
and GND.
4. Measured with rail−to−rail input clock
5. Measured on rising edges at V
DD
÷
2 between any two outputs with equal loading.
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