DATASHEET
TEN CHANNEL HD AUDIO CODEC
Description
The 92HD73E codec is a low power optimized, high fidelity,
10-channel audio codec compatible with Intel’s High
Definition (HD) Audio Interface. The 92HD73E codec
provides stereo 24-bit resolution with sample rates up to
192kHz. Dual SPDIF provides connectivity to consumer
electronic equipment that is WLP compliant. The 92HD73E
provides high quality, HD Audio capability to multimedia
notebook and desktop PC applications.
92HD73E
Software Support
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Intuitive TSI HD Sound graphical user interface that
allows configurability and preference settings
12 band fully parametric equalizer
Constant, system-level effects tuned to optimize a
particular platform can be combined with
user-mode “presets” tailored for specific
acoustical environments and applications
System-level effects automatically disabled when
external audio connections made
Dynamics Processing
Enables improved voice articulation
Compressor/limiter allows higher average volume
level without resonances or damage to speakers.
TSI Vista APO wrapper
Enables multiple APOs to be used with the TSI
Driver
Microphone Beam Forming, Acoustic Echo
Cancellation, and Noise Suppression
Dynamic Stream Switching
Improved multi-streaming user experience with
less support calls
Broad 3
rd
party branded software including
Creative, Dolby, DTS, and SRS
Features
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10 Channels (5 stereo DACs and 2 stereo ADCs)
with 24-bit resolution
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Supports full-duplex 7.1 audio and simultaneous VoIP
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Microsoft WLP premium logo compliant
Optimized and flexible power management with
pop/click mitigation
SPDIF
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48QFP package supports 2 independent S/PDIF Output
converters for WLP compliant HDMI/SPDIF support
40QFN package supports a single SPDIF Out
Both packages support SPDIF Input
48QFP package support for 1.5V and 3.3V with runtime
selection
40QFN package supports 3.3V only
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HDA signaling
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3 adjustable VREF Out pins for microphone bias
High performance analog mixer
9 stereo analog ports with presence detect
capability
Digital and Analog PC Beep to all outputs
3 Integrated headphone amps
Sample rates up to 192kHz
Additional Features on 48QFP package
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Two-pin volume up/down control
Digital microphone input (mono, stereo, or quad array)
4th adjustable VREF Out
Additional 5 GPIOs
48-pin QFP RoHS package
48-pin QFP RoHS package, Industrial Temp
40-pin QFN RoHS package
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Package Options
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TSI™ CONFIDENTIAL
©2014 TEMPO SEMICONDCUTOR, INC.
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V 1.4 09/14
92HD73E
92HD73E
Ten Channel HD Audio Codec
TABLE OF CONTENTS
1. DESCRIPTION .......................................................................................................................... 4
1.1. Overview ............................................................................................................................................4
1.2. Orderable Part Numbers ....................................................................................................................4
1.3. Detailed Description ...........................................................................................................................5
2. CHARACTERISTICS ............................................................................................................... 22
2.1. Electrical Specifications ...................................................................................................................22
2.2. 92HD73E Analog Performance Characteristics ...............................................................................23
3. PORT CONFIGURATIONS ..................................................................................................... 27
4. FUNCTIONAL BLOCK DIAGRAMS ....................................................................................... 28
4.1. 48QFP .............................................................................................................................................28
4.2. 40QFN .............................................................................................................................................29
4.3. Widget Information and Supported Command Verbs ......................................................................30
4.4. Widget List ......................................................................................................................................31
4.5. Pin Configuration Default Register Settings .....................................................................................32
5. WIDGET INFORMATION ........................................................................................................ 34
5.1. Root Node (NID = 00)) .....................................................................................................................35
5.2. AFG Node (NID = 01 .......................................................................................................................36
5.3. Port A Node (NID = 0A) ...................................................................................................................53
5.4. PortB Node (NID = 0B) ....................................................................................................................60
5.5. Port C Node (NID = 0C) ...................................................................................................................67
5.6. Port D Node (NID = 0D) ...................................................................................................................74
5.7. PortE Node (NID = 0E) ....................................................................................................................81
5.8. PortF Node (NID = 0F) .....................................................................................................................88
5.9. PortG Node (NID = 10) ....................................................................................................................93
5.10. PortH Node (NID = 11) ................................................................................................................101
5.11. PortI Node (NID = 12) ..................................................................................................................108
5.12. DMic0 Node (NID = 13) ...............................................................................................................113
5.13. DMic1 Node (NID = 14) ...............................................................................................................117
5.14. DAC0 Node (NID = 15) ................................................................................................................122
5.15. DAC1 Node (NID = 16) ................................................................................................................126
5.16. DAC2 Node (NID = 17) ................................................................................................................131
5.17. DAC3 Node (NID = 18) ................................................................................................................135
5.18. DAC4 Node (NID = 19) ................................................................................................................140
5.19. ADC0 Node (NID = 1A) ................................................................................................................144
5.20. ADC1 Node (NID = 1B) ................................................................................................................149
5.21. DigBeep Node (NID = 1C) ...........................................................................................................153
5.22. Mixer Node (NID = 1D) ................................................................................................................156
5.23. MixerOutVol Node (NID = 1E) .....................................................................................................164
5.24. VolumeKnob Node (NID = 1F) .....................................................................................................167
5.25. ADC0Mux Node (NID = 20) .........................................................................................................171
5.26. ADC1Mux Node (NID = 21) .........................................................................................................175
5.27. Dig0Pin Node (NID = 22) .............................................................................................................180
5.28. Dig1Pin Node (NID = 23) .............................................................................................................185
5.29. Dig2Pin Node (NID = 24) .............................................................................................................190
5.30. SPDIFOut0 Node (NID = 25) .......................................................................................................196
5.31. SPDIFOut1 Node (NID = 26) .......................................................................................................202
5.32. SPDIFIn Node (NID = 27) ............................................................................................................208
5.33. InPort0Mux Node (NID = 28) .......................................................................................................219
5.34. InPort1Mux Node (NID = 29) .......................................................................................................221
5.35. InPort2Mux Node (NID = 2A) .......................................................................................................223
5.36. InPort3Mux Node (NID = 2B) .......................................................................................................226
6. DISCLAIMER ......................................................................................................................... 228
7. PINOUTS ............................................................................................................................... 229
7.1. 48QFP ...........................................................................................................................................229
7.2. 40QFN ...........................................................................................................................................232
8. PACKAGE OUTLINE AND PACKAGE DIMENSIONS ......................................................... 234
8.1. 48QFP Package ...........................................................................................................................234
TSI™ CONFIDENTIAL
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92HD73E
92HD73E
Ten Channel HD Audio Codec
8.2. 40QFN Package ...........................................................................................................................235
8.3. Standard Reflow Profile Data ........................................................................................................235
8.4. Pb Free Process - Package Classification Reflow Temperatures ................................................236
9. DOCUMENT REVISION HISTORY ...................................................................................... 237
LIST OF FIGURES
Figure 1. Multi-channel capture ......................................................................................................................11
Figure 2. Multi-channel timing diagram ..........................................................................................................11
Figure 3. EAPD ..............................................................................................................................................14
Figure 4: Mono Digital Microphone (data is ported to both left and right channels) .......................................16
Figure 5: Stereo Digital Microphone Configuration ........................................................................................16
Figure 6: Quad Digital Microphone Configuration ..........................................................................................17
Figure 7: External Volume Control Circuit ......................................................................................................21
Figure 8. Port Configuration ...........................................................................................................................27
Figure 9. 48QFP Functional Block Diagram ...................................................................................................28
Figure 10. 40QFN Functional Block Diagram ................................................................................................29
Figure 11. Widget Diagram ............................................................................................................................30
Figure 12. 48QFP Pin Assignment ...............................................................................................................229
Figure 13. 40QFN Pin Assignment ..............................................................................................................232
Figure 14. 48QFP Package Drawing ...........................................................................................................234
Figure 15. 40QFN Package Drawing ...........................................................................................................235
Figure 16. Solder Reflow Profile ..................................................................................................................236
LIST OF TABLES
Table 1. Port Functionality ...............................................................................................................................5
Table 2. Analog I/O Port Behavior ...................................................................................................................6
Table 4. SPDIF OUT 0 (Pin 48) Behavior ........................................................................................................7
Table 5. SPDIF OUT 1 (Pin 40) Behavior ........................................................................................................7
Table 6. Input Multiplexers ...............................................................................................................................8
Table 7. Function state vs. AFG power state ...................................................................................................9
Table 10. EAPD Behavior ..............................................................................................................................13
Table 11. Valid Digital Mic Configurations .....................................................................................................15
Table 12. DMIC_CLK and DMIC_0,1 Operation During Power States ..........................................................15
Table 13. GPIO Pin mapping .........................................................................................................................19
Table 14. Electrical Specification: Maximum Ratings ...................................................................................22
Table 15. Recommended Operating Conditions ............................................................................................22
Table 16. 92HD73E Analog Performance Characteristics .............................................................................23
Table 17. High Definition Audio Widget .........................................................................................................31
Table 18. Pin Configuration Default Settings .................................................................................................32
Table 19. Command Format for Verb with 4-bit Identifier ..............................................................................34
Table 20. Command Format for Verb with 12-bit Identifier ............................................................................34
Table 21. Solicited Response Format ............................................................................................................34
Table 22. Unsolicited Response Format ........................................................................................................34
Table 23. 48QFP Pin Table .........................................................................................................................230
Table 24. 40QFN Pin Table .........................................................................................................................233
Table 25. Standard Reflow Profile ...............................................................................................................235
Table 26. Pb-Free Process Reflow ..............................................................................................................236
TSI™ CONFIDENTIAL
©2014 TEMPO SEMICONDCUTOR, INC.
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V 1.4 09/14
92HD73E
92HD73E
Ten Channel HD Audio Codec
1. DESCRIPTION
1.1.
Overview
The 92HD73E is a high fidelity, 10-channel audio codec compatible with the Intel High Definition
(HD) Audio Interface. The 92HD73E codec provides high quality, HD Audio capability to desktop
and multi-media notebook.
The 92HD73E is designed to meet or exceed premium logo requirements for Microsoft’s Windows
Logo Program (WLP) 3.09 and revisions 4 as indicated in WLP 3.09.
The 92HD73E provides stereo 24-bit, full duplex resolution supporting sample rates up to 192kHz by
the DAC and ADC. 92HD73E SPDIF outputs support sample rates of 192kHz, 176.4kHz, 96kHz,
88.2kHz, 48kHz, and 44.1kHz. 92HD73E SPDIF input supports sample rates of 96kHz, 88.2kHz,
48kHz, and 44.1kHz. Additional sample rates are supported by the driver software.
The 92HD73E supports a wide range of desktop and consumer 8/10 channel configurations. The 2
independent SPDIF output interfaces provides connectivity to Consumer Electronic equipment like
Dolby Digital decoders, powered speakers, mini disk drives or to a home entertainment system.
Simultaneous HDMI and SPDIF output is possible.
MIC inputs can be programmed with 0/10/20/30dB boost. For more advanced configurations, the
92HD73E has 8 General Purpose I/O (GPIO) in the 48QFP package.
The port presence detect capabilities allow the codecs to detect when audio devices are connected
to the codec. Load impedance sensing helps identify attached peripherals for easy set-up and a bet-
ter user experience. The fully parametric TSI SoftEQ can be initiated upon headphone jack insertion
and removal for protection of notebook speakers.
The 92HD73E operates with a 3.3V digital supply and a 5V analog supply. It can also work with 1.5V
and 3.3V HDA signaling; the correct signalling level is selected dynamically based on the power sup-
ply voltage on the DVDD-IO pin in the 48QFP package. The 40QFN package allows for 3.3V HDA
signalling.
1.2.
Orderable Part Numbers
92HD73E1X5PRGXB2X*
92HD73E1X5PRGXC1X
92HD73E1T5PRGIC1X
92HD73E2X5NDGXC1X
48QFP
48QFP, Industrial Temp
40QFN
* limited quantities of the B2 available, contact TSI sales.
Add an “8” to the end for tape and reel delivery.
TSI™ CONFIDENTIAL
©2014 TEMPO SEMICONDCUTOR, INC.
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V 1.4 09/14
92HD73E
92HD73E
Ten Channel HD Audio Codec
1.3.
Detailed Description
1.3.1.
Port Functionality
Multi-function (Input / output) ports allow for the highest possible flexibility. 8 bi-directional ports (3
headphone capable) support a wide variety of consumer desktop and mobile system use models.
Port
A
B
C
D
E
F
G
H
CD (Port I)
SPDIF_OUT0
SPDIF_OUT1
SPDIF_IN
DMIC0
DMIC1
Input
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Output
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Headphone
Yes
Yes
Yes
Mic Bias
(Vref pin)
Yes
Yes
Yes
Yes
Input
boost amp
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1
CD
(pseudo differential)
Yes
Yes
Yes
Yes
Table 1. Port Functionality
Yes
Yes
Note
1
: 40dB boost requires using the TSI driver. When the 40dB mic boost feature is enabled, addi-
tional gain increases greater than 6dB may result in significant audio quality degradation of the
microphone audio input. In particular, when the 40dB MIC boost is active, the SNR, THD+N and DC
offset will significantly degrade regardless of the input signal level.
1.3.2.
Port Characteristics
Universal (Bi-directional) jacks are supported on all ports except the CD input. Ports A, B, and D are
designed to drive a set of 32 ohm (nominal) headphones or a 10K (nominal) load with on board
shunt resistance as low as 20K ohms (typical - used to maintain coupling CAP bias.) Line Level out-
puts are intended to drive an external 10K speaker load (nominal) and an on board shunt resistor of
20K-47K (nominal). However, applications may support load impedances of 5K ohms and above.
Input ports are 47K (nominal) at the pin.
DAC full scale output and intended full scale input levels are 1V rms. Line output ports and Head-
phone output ports on 92HD73E may be configured for +3dBV full scale output levels by using a
vendor specific verb.
Output ports are always on to prevent pops/clicks associated with charging and discharging output
coupling capacitors. This maintains proper bias on output coupling caps even in D3 as long as AVDD
is available. Unused ports should be left unconnected. When updating existing designs to use the
92HD73E, ensure that there are no conflicts between the output ports on 92HD73E and existing cir-
cuitry.
TSI™ CONFIDENTIAL
©2014 TEMPO SEMICONDCUTOR, INC.
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92HD73E
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