PRELIMINARY
MX98704
100BASE-TX
PHYSICAL DATA TRANSCEIVER
1.0 FEATURES
•
•
•
•
•
•
•
•
•
•
•
Full-Duplex Operation
Generates 125-Mhz Transmit Clock and 25-Mhz SYMCLK
Converts 5-Bit Parallel Transmit Data to 1-Bit Serial Data
Converts Transmit NRZ Data to NRZI Data
Loopback and Transmitter-Off Modes
Recovers 125-MHz Clock from Incoming serial NRZI Data Stream
Reclocks Incoming Serial NRZI Data Stream Using Recovered Clock
Converts Received Serial Bit Stream to 5-Bit Paralled Form
Converts NRZI data to NRZ
Generates 25-MHz Receive Clock
Package type
-52 PLCC
-52 PQFP
2.0 GENERAL DESCRIPTION
The 100Base-Tx Physical Data Transceiver (PDTR) includes the Physical Data Transmitter (PDT) and the Physical Data
Receiver (PDR). The PDT converts encoded symbols into a serial NRZI data stream. The on-chip PLL generates a bit
rate clock from the TCLKIN or crystal reference. The PDR uses a built-in clock recovery PLL to extract clock information
from the received data stream. The recovered clock is used for serial-to-parallel data conversion.
2.1
FUNCTIONAL BLOCK DIAGRAM
TDAT4-0
Input
Register
Shifter
NRZ/
NRZI
Output
Control
TDH, TDL
SYMCLK
TXEN
XTAL1,
XTAL2
TCLKIN
25 Mhz
Crystal
Oscillator
Clock Multiplier (PLL)
NRZ/
NRZI
RDAT4-0
Output
Register
Shifter
Media
Interface
RDH, RDL
SDO
RSCLK
Divided by 5
Clock & Data
Recovery
(PLL)
Clock
Generator
Control Logic MUX
Normal Mode
Test & Loopback
Signal
Detect
SDI
TEST
LPBKB
Data Transceiver Functions Block Diagram
P/N : PM0351
REV. 1.4, SEP. 15, 1997
1
MX98704
2.1.1
100 BASE-TX HUB APPLICATION
TD(0:4)
MX98741
(Repeator Controller)
RD(0:4)
SD
MX98704
TD(+, -)
SD+
RD(+, -)
MX98702
xformer
8 ports
100 BASE-TX HUB SYSTEM DIAGRAM
2.1.2
10/100-TX NIC APPLICATION
TD(0:4)
MX98713
(MAC)
10BASE-T
TRANSCEIVER
SD
RD(0:4)
MX98704
TD(+, -)
SD+
RD(+, -)
MX98702
TD(+, -)
RX(+, -)
xformer
10/100-TX NIC Application
2.2
SYSTEM APPLICATION
The MX98704 can be used in 100 BASE-TX HUB application, and 10/100-TX NIC application.
2
MX98704
3.0 PIN ASSIGMENT
3.1
PIN ASSIGNMENT-52 LEAD PLASTIC LEADED CHIP CARRIER
GND
NC
VDD
RCP
GND
VDD
GND
VDD
GND
VDD
RT
LP
RSCLK
7
OP1
NC
NC
VDD
SDI
NC
RDL
RDH
VDD
NC
OP2
TDH
TDL
8
1
47
46
MX98704
20
21
34
33
SDO
RDA0
RDA1
RDA2
RDA3
RDA4
TS
TDA0
TDA1
TDA2
TDA3
TDA4
TCKIN
3.2
PIN ASSIGNMENT-52 PQFP
GND
NC
VDD
RCP
GND
VDD
GND
VDD
GND
VDD
RT
LP
RSCLK
GND
VDD
XI
XO
TCP
GND
VDD
GND
VDD
GND
OP3
SYMCLK
TXEN
52
OP1
NC
NC
VDD
SDI
NC
RDL
RDH
VDD
NC
OP2
TDH
TDL
1
40
39
MX98704
13
14
27
26
SDO
RDA0
RDA1
RDA2
RDA3
RDA4
TS
TDA0
TDA1
TDA2
TDA3
TDA4
TCKIN
GND
VDD
XI
XO
TCP
GND
VDD
GND
VDD
GND
OP3
SYMCLK
TXEN
3
MX98704
4.0 PIN DESCRIPTIONS
MX Physicial Data Transceiver (PDTR) Function Pin
PIN (PLCC) PIN (PQFP)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
46
47
48
49
50
51
52
1
2
3
4
5
6
7
8
9
10
11
12
PIN NAME TYPE
GND
VDD
GND
Test
VDD
N/C
GND
OP1
N/C
N/C
VDD
SDI
N/C
RDL
RDH
VDD
NC
OP2
TDH
I
I
I
O
I
O
Parameter Option (GND is recommended)
Transmit Data. These transmit output carrier differential NRZ
data. They can be forced to logical 0 (TDH Low, TDL high) by
asserting the TXEN input.
Transmit Data. These transmit output carrier differential NRZ
data. They can be forced to logical 0 (TDH Low, TDL high) by
asserting the TXEN input.
Ground.
Power Supply. 5V
25MHz Transmit clock. These pins are 25MHz crystal connec-
tion for transmit clock.
25MHz Transmit colck. These pins are 25MHz crystal connec-
tion for transmit clock.
Received Data. (Differential Line Receiver Inputs). These pins
receive NRZI data.
Received Data. (Differential Line Receiver Inputs). These pins
receive NRZI data.
Power Supply. 5V
I
I
power Supply. 5V
Signal Detect Input. This signal indicates that the received
signal is above the detection threshold.
I
I
Ground.
Parameter Option (GND is recommended)
I
I
I
O
I
DESCRIPTION
Ground.
Power Supply. 5V
Ground.
Receiver Filter.
Power Supply. 5V
20
13
TDL
O
21
22
23
24
14
15
16
17
GND
VDD
XTALI
XTALO
I
I
I
O
4
MX98704
PIN (PLCC) PIN (PQFP) PIN NAME
25
26
27
28
29
30
31
32
33
18
19
20
21
22
23
24
25
26
Test
GND
VDD
GND
VDD
GND
OP3
SYMCLK
TXEN
TYPE
O
I
I
I
I
I
O
O
I
DESCRIPTION
Transmit Filter.
Ground.
Power Supply. 5V
Ground.
Power Supply. 5V
Ground.
Parameter Option (GND is recommended)
Local Symbol Clock. This pin supplies the frequency reference
to the transmit logic. It is the buffered 25MHz oscillator output.
Transmit Enable. When held LOW, the TDH output is forced
LOW, and TDL output is forced HIGH so that the transmitter will
output logical 0. This TTL-level signal has an internal pullup
resistor.
Transmit Clock In. This pin is a 25Mhz optional clock input.
Transmit Data. These five inputs are 4B/5B encoded transmit
data symbols, latched by the rising edge of SYMCLK. TDAT4
is the Most Significant Bit.
Three-State. While this pin input is low, the interface output pins
are forced into the high-impedance state. Pins controlled by this
signal are PDAT4-0, SDO, BYTCLK, SYMCLK and RSCLK.
This TTL-level signal has an internal pullup resistor.
Receive Data. These 5-bit parallel data symbols from trans-
ceiver are clocked by the falling edge of RSCLK and carry the
NRZ data symbols to the controller. RDAT4 is the Most
Significant Bit.
Signal Detect Output. SDO is the SDI input Asynchronized by
RSCLK. It has the same logical sense as SDI.
Recovered Symbol Clock. This is a 25MHz clock, which is
derived from the receive clock synchronization PLL circuit. It is
synchronous to the received serial data, and is the recovered bit
clock divided-by-five.
Loopback. (Active LOW) The function is used during system
loopback test to bypass the transmission medium. This TTL-
level signal has an internal pullup resistor.
Test Mode Enable. When asserted, the PDTR is in Test mode.
For normal operation, TEST pin must be tied High. This TTL-
level signal has an internal pullup resistor.
Power Supply. 5V
Ground.
Power Supply. 5V
34
35-39
27
28-32
TCLKIN
TDAT4-0
I
I
40
33
TSB
I
41-45
34-38
RDAT4-0
O
46
47
39
40
SDO
RSCLK
O
O
48
41
LPBKB
I
49
42
TEST
I
50
51
52
43
44
45
VDD
GND
VDD
I
I
I
5
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