The PL602-XX is the smallest, high performance, lowest power differential output clock IC available for HCSL
timing applications. PL602-XX offers -130dBc at 10kHz offset at 100MHz, with a very low jitter
(2 ps TIE RMS), making it ideal for HCSL applications requiring small size and low power.
BLOCK DIAGRAM
OE
XIN, FIN
XOUT
PIN DESCRIPTION
Name
XIN
FIN
GND
CLK[0:1]
VDD
DNC
OE
XOUT
Pin #
SOP
1
-
2
3,4
5
6
7
8
SOT23
-
3
2
1,6
5
-
4
-
Type
I
I
P
O
P
-
I
O
Description
Crystal input (SOP package only)
Reference clock input (SOT23 package only)
GND connection
Differential clock outputs [note:CLK0=~CLK1]
VDD connection
Do not connect
Output enable (OE) input. Internal 60KΩ pull up resistor.
Crystal output pin.
Xtal
Osc
Phase
Locked
Loop
Q
QB
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 02/08/11 Page 1
PL602-XX
HCSL Compatible Clock Generator for PCI Express
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Soldering Temperature
Storage Temperature
Ambient Operating Temperature*
T
S
-65
-40
SYMBOL
V
DD
V
I
V
O
MIN.
-0.5
-0.5
-0.5
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
260
150
+85
UNITS
V
V
V
C
C
C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
Crystal Input Frequency
Input (F
IN
) Frequency
Input (F
IN
) Signal Amplitude Internally AC coupled
Output Frequency
Output Enable Time
Output Disable Time
Settling Time
VDD Sensitivity
Output Rise Time
Output Fall Time
Skew Between Outputs
Duty Cycle
Period Jitter, peak-to-peak
Cycle-to-Cycle, RMS
Cycle-to-Cycle, peak
TIE, RMS
OE Function; Ta=25º C, Add one clock
period to this measurement for a usable
clock output.
OE Function; Ta=25º C
At power-up (V
DD
> 2.25V)
Frequency vs. V
DD
, ±10%
10/90%V
OH
90/10%V
OH
Measured at 50% V
OH
At V
DD
/2
- With capacitive decoupling between V
DD
and GND
- At 100MHz
- 20,000 samples measured
45
50
28
9
25
2
-2
0.3
0.3
0.9
25
CONDITIONS
Fundamental Crystal
MIN.
TYP.
25
25
V
DD
200
10
10
10
2
0.5
0.5
250
55
MAX.
UNITS
MHz
MHz
Vpp
MHz
ns
ns
ms
ppm
ns
ns
ps
%
ps
ps
ps
ps
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 02/08/11 Page 2
PL602-XX
HCSL Compatible Clock Generator for PCI Express
DC SPECIFICATIONS
PARAMETERS
Supply Current, Dynamic
Operating Voltage
Output Low Voltage
Output High Voltage
Output Current
SYMBOL
I
DD
V
DD
V
OL
V
OH
I
OSD
HCSL termination,
(RS = 150Ω, RT = 49.9Ω) 3.3V
(RS = 100Ω, RT = 49.9Ω) 2.5V
CONDITIONS
At 100MHz, No Load
2.25
0.65
13
0.75
15
MIN.
TYP.
25
3.63
0.05
0.85
17
MAX.
UNITS
mA
V
V
V
mA
CRYSTAL SPECIFICATIONS
PARAMETERS
Fundamental Crystal Resonator Frequency
Crystal Loading Rating
Maximum Sustainable Drive Level
Operating Drive Level
Crystal Shunt Capacitance
Effective Series Resistance, Fundamental
C0
ESR
100
6
45
SYMBOL
F
XIN
C
L (x ta l)
MIN.
TYP.
25
18
500
MAX.
UNITS
MHz
pF
W
W
pF
Ω
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 02/08/11 Page 3
PL602-XX
HCSL Compatible Clock Generator for PCI Express
PCI EXPRESS/HCSL COM PATIBLE LAYOUT GUIDELINES
Figure 1 below describes how to terminate the complementary LVCMOS outputs of PL602-XX for use with HCSL
inputs.
LVCMOS Output
Rs
50 Ohm line
Input
Rt
Complementary
LVCMOS Output
Rs
50 Ohm line
Rt
Complementary
Input
HCSL
0.75V
0V
3.3V
0V
Component Selection
For 3.3V Operation
Rs = 150 Ohm
Rt = 50 Ohm
For 2.5V Operation
Rs = 100 Ohm
Rt = 50 Ohm
Notes:
Place Rs as close to the LVCMOS outputs as possible.
Place Rt as close to the HCSL inputs as possible.
Figure 1
PCB LAYOUT CONSIDERATIONS FOR PERFORMANCE OPTIMIZATION
The following guidelines are to assist you with a performance optimized PCB design:
-
Keep all the PCB traces to PL602-XX as short as
possible, as well as keeping all other traces as far away
from it as possible.
-
Place the crystal as close as possible to both crystal
pins of the device. This will reduce the cross-talk
between the crystal and the other signals.
-
Separate crystal pin traces from the other signals on the
PCB, but allow ample distance between the two crystal
pin traces.
-
Place a 0.01µF~0.1µF decoupling capacitor between
VDD and GND, on the component side of the PCB,
close to the VDD pin. It is not recommended to place
this component on the backside of the PCB.
-
It is highly recommended to keep the VDD and GND
traces as short as possible.
-
When connecting long traces (> 1 inch) to a CMOS
output, it is important to design the traces as a
transmission line or ‘stripline’, to avoid reflections or
ringing. In this case, the CMOS output needs to be
matched to the trace impedance. Usually ‘striplines’ are
designed for 50Ω impedance and CMOS outputs
usually have lower than 50Ω impedance so matching
can be achieved by adding a resistor in series with the
CMOS output pin to the ‘stripline’ trace.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 02/08/11 Page 4
PL602-XX
HCSL Compatible Clock Generator for PCI Express
PACKAGE DRAWINGS (GREEN PACKAGE COM PLIANT)
SOP-8L
Symbol
A
A1
A2
B
C
D
E
H
L
e
SOT23-6L
Dimension in MM
Min.
Max.
1.05
1.35
0.05
0.15
1.00
1.20
0.30
0.50
0.08
0.20
2.80
3.00
1.50
1.70
2.60
3.0
0.35
0.55
0.95 BSC
Dimension in MM
Min.
Max.
1.35
1.75
0.10
0.25
1.25
1.50
0.33
0.53
0.19
0.27
4.80
5.00
3.80
4.00
5.80
6.20
0.40
0.89
1.27 BSC
E
H
D
A2 A
A1
e
b
C
L
Symbol
A
A1
A2
B
C
D
E
H
L
e
E
H
D
A2 A
A1
e
b
C
L
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
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