NCP458R, NCP459
4 A Single Load Switch for
Low Voltage Rail
The NCP458R and NCP459 are power load switch with very low
Ron NMOSFET controlled by external logic pin, allowing
optimization of battery life, and portable device autonomy.
Indeed, thanks to a best in class current consumption optimization
with NMOS structure, leakage currents are drastically decreased.
Offering optimized leakages isolation on the ICs connected on the
battery.
Output discharge path is proposed, in the NCP459 version , to
eliminate residual voltages on the external components connected on
output pin.
Reverse voltage protection, from OUT to IN is offered in the
NCP458R version.
Proposed in wide input voltage range from 0.75 V to 5.5 V, and a
very small CSP8 1 x 2 mm
2
.
Features
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MARKING
DIAGRAM
WLCSP8
CASE 567HD
A
Y
WW
G
XXXX
AYWWG
= Assembly Location
= Year
= Work Week
= Pb−Free Package
PINOUT
1
2
•
•
•
•
•
•
•
•
•
•
•
•
•
0.75 V − 5.5 V Operating Range
11 mW N−MOSFET
Vbias Rail Input
DC Current up to 4 A
Output Auto−Discharge Option
Reverse Blocking Option
Active High EN Pin
CSP8, 1 x 2 mm
2
, Pitch 0.5 mm
A
EN
GATE
B
IN
OUT
C
IN
OUT
Typical Applications
Notebooks
Tablets
Wireless
Mobile Phones
Digital Cameras
D
VBIAS
GND
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information on page 12 of
this data sheet.
Vcc
V+
LS
NCP458−459
SMPS
DCDC Converter
or
LDO
ENx
B1
OUT
C1
IN
OUT
A2
IN
D1
Gate EN
Vbias GND
B2
C2
A1
D2
Platform IC’n
EN
0
Figure 1. Typical Application Schematic
©
Semiconductor Components Industries, LLC, 2014
1
June, 2014 − Rev. 1
Publication Order Number:
NCP458R/D
NCP458R, NCP459
LS
NCP458−459
DCDC Converter
or
LDO
B1
C1
A2
D1
IN
OUT
IN
OUT
Gate
EN
Vbias GND
B2
C2
A1
D2
Platform IC’n
ENx
EN
0
Figure 2. Application Schematic with Vbias Connected to IN and No Gate Delay
PIN FUNCTION DESCRIPTION
Pin Name
EN
IN
VBIAS
GATE
OUT
GND
Pin Number
A1
B1, C1
D1
A2
B2, C2
D2
Type
INPUT
POWER
POWER
INPUT
POWER
POWER
Description
Enable input, logic high turns on power switch .
Load−switch input pin.
External supply voltage input.
OUT pin slew rate control (t
rise
).
Load−switch output pin.
Ground connection.
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2
NCP458R, NCP459
BLOCK DIAGRAMS
IN: B1, C1
OUT : B2, C 2
GATE : A2
Gate driver
Control
logic
&
Charge
Pump
EN: A1
GND : D2
VBIAS : D1
Figure 3. NCP458R Block Diagram
IN: B1, C1
OUT : B2 , C 2
GATE : A2
Gate driver
Control
logic
&
Charge
Pump
GND : D 2
VBIAS : D 1
EN : A1
Figure 4. NCP459 Block Diagram
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3
NCP458R, NCP459
MAXIMUM RATINGS
Rating
IN, OUT, EN, VBIAS, GATE Pins: (Note 1)
From IN to OUT Pins: Input/Output (Note 1) NCP459
From IN to OUT Pins: Input/Output (Note 1) NCP458R
Human Body Model (HBM) ESD Rating are (Note 2)
Machine Model (MM) ESD Rating are (Note 2)
Latch−up protection (Note 3)
− Pins IN, OUT, EN, VBIAS and GATE
Maximum Junction Temperature
Storage Temperature Range
Moisture Sensitivity (Note 4)
Symbol
V
EN,
V
IN ,
V
OUT,
V
BIAS,
V
GATE
V
IN ,
V
OUT
V
IN ,
V
OUT
ESD HBM
ESD MM
LU
T
J
T
STG
MSL
Value
−0.3 to +6.5
0 to + 6.5
±6.5
2000
200
100
−40 to + 125
−40 to + 150
Level 1
Unit
V
V
V
V
V
mA
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. According to JEDEC standard JESD22−A108.
2. This device series contains ESD protection and passes the following tests:
Human Body Model (HBM)
±2.0
kV per JEDEC standard:
JESD22−A114 for all pins.
Machine Model (MM)
±250
V per JEDEC standard: JESD22−A115 for all pins.
3. Latch up Current Maximum Rating:
±100
mA per JEDEC standard: JESD78 class II.
4. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020.
OPERATING CONDITIONS
Symbol
V
IN
V
EN
V
BIAS
T
A
C
IN
C
OUT
R
qJA
Parameter
Operational Power Supply
Enable Voltage
Bias voltage (V
BIAS
≥
best of V
IN,
V
OUT
)
Ambient Temperature Range
Decoupling input capacitor
Decoupling output capacitor
Thermal Resistance Junction to Air
DC current
I
OUT
AC current 1 ms @ 217 Hz
AC current 100
ms
spike
P
D
Power Dissipation Rating (Note 6)
0.315
CSP8 (Note 5)
Conditions
Min
0.75
0
1.2
− 40
100
100
90
4
4.5
5
15
25
Typ
Max
5.5
5.5
5.5
+ 85
Unit
V
V
V
°C
nF
nF
°C/W
A
A
A
W
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. The R
qJA
is dependent of the PCB heat dissipation and thermal via.
6. The maximum power dissipation (
PD
) is given by the following formula:
P
D
+
T
JMAX
*
T
A
R
qJA
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4
NCP458R, NCP459
ELECTRICAL CHARACTERISTICS
Min & Max Limits apply for T
A
between −40°C to +85°C for V
IN
between 0.75 V and 5.5 V,
and V
BIAS
between 1.2 V and 5.5 V (Unless otherwise noted). Typical values are referenced to T
A
= + 25°C, V
IN
= 3.3 V and
V
BIAS
= 5 V (Unless otherwise noted).
Symbol
POWER SWITCH
V
IN
= V
BIAS
= 5.5 V
T
A
= 25°C
T
J
= 125°C
T
A
= 25°C
T
J
= 125°C
T
A
= 25°C
T
J
= 125°C
T
A
= 25°C
T
J
= 125°C
T
A
= 25°C
T
J
= 125°C
T
A
= 25°C
T
J
= 125°C
T
A
= 25°C
T
J
= 125°C
EN = low, NCP459
230
17
14
13
13
12
11
11
20
24
20
24
20
24
20
24
20
24
24
30
30
35
300
W
mW
Parameter
Conditions
Min
Typ
Max
Unit
V
IN
= V
BIAS
= 3.3 V
V
IN
= V
BIAS
= 1.8 V
Static drain−source
on−state resistance
for each rail
R
DS(on)
V
IN
= V
BIAS
= 1.5 V
V
IN
= V
BIAS
= 1.2 V
V
IN
= 1.0 V
V
BIAS
= 1.2 V
V
IN
= 0.8 V
V
BIAS
= 1.2 V
R
DIS
TIMINGS
Output rise time
From 10% to 90% of
V
OUT
Enable time From En
V
ih
to 10% of V
OUT
Fall Time. From 90%
to 10% of V
OUT
Disable time
Output rise time
From 10% to 90% of
V
OUT
Enable time
From En V
ih
to 10%
of V
OUT
Output fall time
From 90% to 10% of
V
OUT
V
IN
= 3.3 V
C
LOAD
= 1
mF,
R
LOAD
= 25
W
V
IN
= 5 V
C
LOAD
= 1
mF,
R
LOAD
= 25
W
Output discharge
path
No cap on GATE pin
Gate capacitor = 1 nF
Gate capacitor = 10 nF
Without Cgate
With 1 nF on Gate
0.26
1.5
15
10
60
50
ms
ms
ms
ms
0.5
ms
ms
ms
ms
120
ms
ms
T
R
T
en
T
F
Tdis
From EN to 90% Vout
No cap on GATE pin
Gate capacitor = 1 nF
Gate capacitor = 10 nF
Without Cgate, NCP459
Without Cgate, NCP458R
With 1 nF on Gate
75
0.25
1
10
20
90
114
60
50
150
T
R
T
en
T
F
No cap on GATE pin
T
R
Output rise time From
10% to 90% of V
OUT
Enable time From En
V
ih
to 10% of V
OUT
Output fall time From
90% to 10% of V
OUT
V
IN
= 1.8 V
C
LOAD
= 1
mF,
R
LOAD
= 25
W
Gate capacitor = 1 nF
Gate capacitor = 10 nF
Without Cgate
With 1 nF on Gate
0.12
0.6
5.5
15
85
35
ms
ms
ms
ms
T
en
T
F
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Parameters are guaranteed for C
LOAD
and R
LOAD
connected to the OUT pin with respect to the ground
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