CY7C1380D
CY7C1380F
CY7C1382D
18-Mbit (512K × 36/1M × 18)
Pipelined SRAM
18-Mbit (512K × 36/1M × 18) Pipelined SRAM
Features
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Functional Description
The CY7C1380D/CY7C1380F/CY7C1382D SRAM integrates
524,288 × 36 and 1,048,576 × 18 SRAM cells with advanced
synchronous peripheral circuitry and a two-bit counter for
internal burst operation. All synchronous inputs are gated by
registers controlled by a positive edge triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE
1
), depth-expansion
chip enables (CE
2
and CE
3
), burst control inputs (ADSC, ADSP,
and ADV), write enables (BW
X
, and BWE), and global write
(GW). Asynchronous inputs include the output enable (OE) and
the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when address strobe processor (ADSP) or address strobe
controller (ADSC) are active. Subsequent burst addresses can
be internally generated as they are controlled by the advance pin
(ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle. This part supports byte write
operations (see
Pin Definitions on page 6
and
Truth Table on
page 10
for further details). Write cycles can be one to two or four
bytes wide as controlled by the byte write control inputs. GW
when active LOW causes all bytes to be written.
The CY7C1380D/CY7C1380F/CY7C1382D operates from a
+3.3 V core power supply while all outputs operate with a +2.5
or +3.3 V power supply. All inputs and outputs are
JEDEC-standard and JESD8-5-compatible.
For a complete list of related documentation, click
here.
Supports bus operation up to 250 MHz
Available speed grades are 250, 200, and 167 MHz
Registered inputs and outputs for pipelined operation
3.3 V core power supply
2.5 V or 3.3 V I/O power supply
Fast clock-to-output times
❐
2.6 ns (for 250 MHz device)
Provides high performance 3-1-1-1 access rate
User selectable burst counter supporting Intel
®
Pentium
®
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed write
Asynchronous output enable
Single cycle chip deselect
CY7C1380D/CY7C1382D is available in JEDEC-standard
Pb-free 100-pin TQFP package; CY7C1380F is available in
non Pb-free 165-ball FBGA package
IEEE 1149.1 JTAG-Compatible Boundary Scan
ZZ sleep mode option
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Selection Guide
Description
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
250 MHz
2.6
350
70
200 MHz
3.0
300
70
167 MHz
3.4
275
70
Unit
ns
mA
mA
Errata:
For information on silicon errata, see
“Errata”
on page 32. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-05543 Rev. *S
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 29, 2016
Not Recommended for New Designs.
CY7C1380D
CY7C1380F
CY7C1382D
Logic Block Diagram – CY7C1380D/CY7C1380F
A0, A1, A
ADDRESS
REGISTER
2
A
[1:0]
MODE
ADV
CLK
Q1
ADSC
ADSP
BW
D
DQ
D ,
DQP
D
BYTE
WRITE REGISTER
DQ
C ,
DQP
C
BYTE
WRITE REGISTER
DQ
B ,
DQP
B
BYTE
WRITE REGISTER
DQ
A ,
DQP
A
BYTE
WRITE REGISTER
BURST
COUNTER
CLR
AND
LOGIC
Q0
DQ
D
,DQP
D
BYTE
WRITE DRIVER
BW
C
MEMORY
ARRAY
BW
B
DQ
B ,
DQP
B
BYTE
WRITE DRIVER
DQ
A ,
DQP
A
BYTE
WRITE DRIVER
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQP
A
DQP
B
DQP
C
DQP
D
BW
A
BWE
GW
CE
1
CE
2
CE
3
OE
ENABLE
REGISTER
PIPELINED
ENABLE
INPUT
REGISTERS
ZZ
SLEEP
CONTROL
Logic Block Diagram – CY7C1382D
A0, A1, A
ADDRESS
REGISTER
2
ADV
CLK
BURST Q1
COUNTER AND
LOGIC
ADSC
BW
B
DQ
B,
DQP
B
WRITE REGISTER
DQ
B,
DQP
B
WRITE DRIVER
MEMORY
ARRAY
SENSE
OUTPUT
OUTPUT
BUFFERS
BW
A
BWE
GW
CE
1
CE2
CE3
OE
DQ
A,
DQP
A
WRITE REGISTER
DQ
A,
DQP
A
WRITE DRIVER
DQs
DQP
A
DQP
B
INPUT
ENABLE
REGISTER
PIPELINED
ENABLE
ZZ
SLEEP
CONTROL
Document Number: 38-05543 Rev. *S
Page 2 of 38
Not Recommended for New Designs.
DQ
C ,
DQP
C
BYTE
WRITE DRIVER
CY7C1380D
CY7C1380F
CY7C1382D
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 6
Functional Overview ........................................................ 8
Single Read Accesses ................................................ 8
Single Write Accesses Initiated by ADSP ................... 8
Single Write Accesses Initiated by ADSC ................... 8
Burst Sequences ......................................................... 8
Sleep Mode ................................................................. 9
Interleaved Burst Address Table ................................. 9
Linear Burst Address Table ......................................... 9
ZZ Mode Electrical Characteristics .............................. 9
Truth Table ...................................................................... 10
Truth Table for Read/Write ............................................ 11
Truth Table for Read/Write ............................................ 11
IEEE 1149.1 Serial Boundary Scan (JTAG [13]) ........... 12
Disabling the JTAG Feature ...................................... 12
Test Access Port (TAP) ............................................. 12
PERFORMING A TAP RESET .................................. 12
TAP REGISTERS ...................................................... 12
TAP Instruction Set ................................................... 13
TAP Controller State Diagram ....................................... 14
TAP Controller Block Diagram ...................................... 15
TAP Timing ...................................................................... 16
TAP AC Switching Characteristics ............................... 16
3.3 V TAP AC Test Conditions ....................................... 17
3.3 V TAP AC Output Load Equivalent ......................... 17
2.5 V TAP AC Test Conditions ....................................... 17
2.5 V TAP AC Output Load Equivalent ......................... 17
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 17
Identification Register Definitions ................................ 18
Scan Register Sizes ....................................................... 18
Identification Codes ....................................................... 18
Boundary Scan Order .................................................... 19
Maximum Ratings ........................................................... 20
Operating Range ............................................................. 20
Electrical Characteristics ............................................... 20
Capacitance .................................................................... 21
Thermal Resistance ........................................................ 21
AC Test Loads and Waveforms ..................................... 22
Switching Characteristics .............................................. 23
Switching Waveforms .................................................... 24
Ordering Information ...................................................... 28
Ordering Code Definitions ......................................... 28
Package Diagrams .......................................................... 29
Acronyms ........................................................................ 31
Document Conventions ................................................. 31
Units of Measure ....................................................... 31
Errata ............................................................................... 32
Part Numbers Affected .............................................. 32
Product Status ........................................................... 32
Ram9 Sync ZZ Pin
& JTAG Issues Errata Summary ...................................... 32
Document History Page ................................................. 34
Sales, Solutions, and Legal Information ...................... 38
Worldwide Sales and Design Support ....................... 38
Products .................................................................... 38
PSoC® Solutions ...................................................... 38
Cypress Developer Community ................................. 38
Technical Support ..................................................... 38
Document Number: 38-05543 Rev. *S
Page 3 of 38
Not Recommended for New Designs.
CY7C1380D
CY7C1380F
CY7C1382D
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout (3-Chip Enable)
[1]
CY7C1380D (512K × 36)
CY7C1382D (1M × 18)
Note
1. Errata:
The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see
“Errata”
on page 32.
Document Number: 38-05543 Rev. *S
Page 4 of 38
Not Recommended for New Designs.
CY7C1380D
CY7C1380F
CY7C1382D
Pin Configurations
(continued)
Figure 2. 165-ball FBGA (13 × 15 × 1.4 mm) pinout (3-Chip Enable)
[2, 3]
CY7C1380F (512K × 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC/288M
NC/144M
DQP
C
DQ
C
DQ
C
DQ
C
DQ
C
NC
DQ
D
DQ
D
DQ
D
DQ
D
DQP
D
NC
MODE
2
A
A
NC
DQ
C
DQ
C
DQ
C
DQ
C
NC
DQ
D
DQ
D
DQ
D
DQ
D
NC
NC/72M
NC/36M
3
CE
1
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
4
BW
C
BW
D
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
5
BW
B
BW
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
6
CE
3
CLK
7
BWE
GW
8
ADSC
OE
9
ADV
ADSP
10
A
A
NC/1G
DQ
B
DQ
B
DQ
B
DQ
B
NC
DQ
A
DQ
A
DQ
A
DQ
A
NC
A
A
11
NC
NC/576M
DQP
B
DQ
B
DQ
B
DQ
B
ZZ
DQ
A
DQ
A
DQ
A
DQ
A
DQP
A
A
A
DQ
B
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
A1
A0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
A
Notes
2. Errata:
The ZZ ball (H11) needs to be externally connected to ground. For more information, see
“Errata”
on page 32.
3. Errata:
The JTAG testing should be performed with these devices in BYPASS mode as the JTAG functionality is not guaranteed. For more information, see
“Errata”
on page 32.
Document Number: 38-05543 Rev. *S
Page 5 of 38
Not Recommended for New Designs.
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