NCP1575
Low Voltage Synchronous
Buck Controller with
Adjustable Switching
Frequency
The NCP1575 is a low voltage buck controller. It provides the
control for a DC−DC power solution producing an output voltage as
low as 0.980 V over a wide current range. It contains all required
circuitry for a synchronous NFET buck regulator using the V
2
t
control method to achieve the fastest possible transient response and
best overall regulation. The NCP1575 operates at a default switching
frequency of 200 kHz, but switching frequency is user−programmable
with an additional resistor between R
OSC
and ground. This device
provides undervoltage lockout protection, soft−start, and built−in
adaptive nonoverlap and is assembled in an SOIC−8 package.
The NCP1575−based solution requires a bias supply of 12 V, and it
can convert from a bulk power supply ranging from 2 V to 12 V.
Conversion from bulk supplies greater than 7 V is best accomplished
by using an external doubler circuit to raise the enhancement voltage
for the external NFET switches.
Features
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MARKING
DIAGRAM
8
8
1
SOIC−8
D SUFFIX
CASE 751
1
1575
ALYW
A
L
Y
W
= Assembly Location
= Wafer Lot
= Year
= Work Week
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Pb−Free Packages are Available
0.980 V
±1.0%
Reference Voltage
V
2
Control Topology
200 ns Transient Response
Programmable Soft−Start
40 ns Gate Rise and Fall Times (3.3 nF Load)
Adaptive FET Nonoverlap Time
Default 200 kHz Oscillator Frequency (No External
Resistor Required)
User−Programmable Oscillator Frequency (One External
Resistor Required)
Undervoltage Lockout
On/Off Control Through Use of the COMP Pin
Overvoltage Protection through Synchronous MOSFETs
Synchronous N−Channel Buck Design
“12 V Only” or Dual Supply Operation
PIN CONNECTIONS
V
CC
R
OSC
NC
COMP
1
8
GND
V
FB
GATE(L)
GATE(H)
ORDERING INFORMATION
Device
NCP1575D
NCP1575DG
NCP1575DR2
NCP1575DR2G
Package
SOIC−8
SOIC−8
(Pb−Free)
SOIC−8
SOIC−8
(Pb−Free)
Shipping
†
98 Units/Rail
98 Units/Rail
2500 Tape & Reel
2500 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2004
1
November, 2004 − Rev. 6
Publication Order Number
NCP1575/D
NCP1575
12 V
D3
BAS20HT1
R1
470
D2
BAV99LT1
C11
0.1
mF
L1
1.0
mH
+
C1
1000
mF/16
V
+
C2
1000
mF/16
V
C3
0.1
mF
U1
C9
0.01
mF
GND
V
FB
GATE(L)
GATE(H)
Q2
NTD110N02R
NCP1575
L2
4.7
mH
Q1
NTD60N02R
2.5 V/
10 A
Q3
MMBT3904LT1
D1
18 V Zener
BZX84C18V
V
CC
C4
1.0
mF
R3
Option
R
OSC
NC
COMP
C11
0.1
mF
+
+
C5
C6
1000
mF
1000
mF
R6
5.11 k
C10
4700 pF
C8
104
R5
3.32 k
0.98 V
Figure 1. 12 V Only Applications Diagram, 12 V to 2.5 V Conversion at 10 A
5V
12 V
33
mF
8 V/1.6 A RMS
×
2
Specialty Polymer
60 mW ESR
1.2 V/ 10 A
56
mF
4 V/1.6 A RMS
×
2
Specialty Polymer
40 mW ESR
NTD4302
1.4
mH
NCP1575
V
CC
R
OSC
NC
COMP
33 k
0.1
mF
0.1
mF
GND
V
FB
GATE(L)
GATE(H)
1000 pF
NTD4302
2.26 k
10 k
Figure 2. 12 V/5 V Applications Diagram, 350 kHz, 5 V to 1.2 V Conversion at 10 A
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2
NCP1575
12 V
L1
1.0
mH
R7
D1
5.6 V Zener
BZX84C5V6
R1
15
C4
205
R3
Option
open
15
+
C1
1000
mF/16
V
+
C2
1000
mF/16
V
C3*
0.033
mF
2.5 V/
6.0 A
Q1
NTD30N02
L2
2.4
mH
Q4
NTD30N02
+
+
D2
BAV99LT1
U1
V
CC
R
OSC
NC
COMP
C11
0.1
mF
R5
3.3 k
GND
V
FB
GATE(L)
GATE(H)
NCP1575
C9
10000 pF
C5
C6
1000
mF
1000
mF
C8
104
0.98 V
R6
5.1 k
C10
4700 pF
*C3 value is dependent on MOSFET
gate drive current. Incorrect values
may cause poor V
CC
regulation or
excessive power dissipation in D1.
Figure 3. 12 V Only Applications Diagram, 12 V to 2.5 V Conversion at 6 A
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NCP1575
MAXIMUM RATINGS
Rating
Operating Junction Temperature
Storage Temperature Range
ESD Susceptibility (Human Body Model)
ESD Susceptibility (Charged Device Model)
Lead Temperature Soldering:
Moisture Sensitivity Level
Package Thermal Resistance, SOIC−8:
Junction−to−Case, R
qJC
Junction−to−Ambient, R
qJA
Reflow: (Note 1)
Value
150
−65 to 150
2.0
200
230 peak
2
48
165
Unit
°C
°C
kV
V
°C
−
°C/W
°C/W
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. 60 second maximum above 183°C.
MAXIMUM RATINGS
Pin Name
IC Power Input
Compensation Capacitor
Voltage Feedback Input
Frequency Adjust
High−Side FET Driver
Low−Side FET Driver
Ground
Symbol
V
CC
COMP
V
FB
R
OSC
GATE(H)
GATE(L)
GND
V
MAX
20 V
6.0 V
6.0 V
6.0 V
20 V
20 V
0.5 V
V
MIN
−0.5 V
−0.5 V
−0.5 V
−0.5 V
−0.5 V, −2.0 V for 50 ns
−0.5 V, −2.0 V for 50 ns
−0.5 V
I
SOURCE
N/A
10 mA
1.0 mA
1.0 mA
1.5 A Peak, 200 mA DC
1.5 A Peak, 200 mA DC
1.5 A Peak, 450 mA DC
I
SINK
1.5 A Peak, 450 mA DC
10 mA
1.0 mA
1.0 mA
1.5 A Peak, 200 mA DC
1.5 A Peak, 200 mA DC
N/A
ELECTRICAL CHARACTERISTICS
(0°C < T
J
< 125°C, 9.0 V < V
CC
< 20 V, C
GATE(H)
= C
GATE(L)
= 3.3 nF,
C
COMP
= 0.1
mF,
R
OSC
= 74 kW; unless otherwise specified.) Note 2
Characteristic
Error Amplifier
V
FB
Bias Current
COMP Source Current
COMP Sink Current
Reference Voltage
V
FB
= 0 V
COMP = 1.5 V, V
FB
= 0.8 V
COMP = 1.5 V, V
FB
= 1.2 V
COMP = V
FB
T
J
< 25°C
V
FB
= 0.8 V
V
FB
= 1.2 V
COMP = 1.2 V, V
CC
= 6.9 V
−
−
−
−
−
−
−
15
15
0.970
0.965
2.4
−
0.5
0.1
−
−
−
−
−
0.4
30
30
0.980
0.980
3.1
0.1
1.2
0.25
98
20
70
32
2.5
2.0
60
60
0.990
0.995
−
0.2
−
0.3
−
−
−
−
−
mA
mA
mA
V
V
V
V
mA
V
dB
kHz
dB
mmho
MW
Test Conditions
Min
Typ
Max
Unit
COMP Max Voltage
COMP Min Voltage
COMP Fault Discharge Current at UVLO
COMP Fault Discharge Threshold to
Reset UVLO
Open Loop Gain
Unity Gain Bandwidth
PSRR @ 1.0 kHz
Output Transconductance
Output Impedance
2. Characteristics at temperature extremes are guaranteed via correlation using quality statistical control methods.
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NCP1575
C
COMP
= 0.1
mF,
R
OSC
= 74 kW; unless otherwise specified.) Note 3
Characteristic
GATE(H) and GATE(L)
Rise Time
Fall Time
GATE(H) to GATE(L) Delay
GATE(L) to GATE(H) Delay
Minimum Pulse Width
High Voltage (AC)
Low Voltage (AC)
GATE(H)/(L) Pull−Down
PWM Comparator
PWM Comparator Offset
Ramp Max Duty Cycle
Artificial Ramp
Transient Response
V
FB
Input Range
Oscillator
Switching Frequency
R
OSC
Not Used
R
OSC
= 74 kW
170
240
200
280
230
320
kHz
kHz
V
FB
= 0 V, Increase COMP Until GATE(H)
Starts Switching
−
Duty Cycle = 50%, R
OSC
= 74 kW
COMP = 1.5 V, V
FB
20 mV Overdrive. Note 4
Note 4
0.415
−
50
−
0
0.465
80
63
200
−
0.525
−
75
300
1.4
V
%
mV
ns
V
1.0 V < GATE(L), GATE(H) < V
CC
− 2.0 V,
V
CC
= 12 V
V
CC
− 2.0 V < GATE(L), GATE(H) < 1.0 V,
V
CC
= 12 V
GATE(H) < 2.0 V, GATE(L) > 2.0 V
GATE(L) < 2.0 V, GATE(H) > 2.0 V
GATE(X) = 4.0 V
Measure GATE(L) or GATE(H)
0.5 nF < C
GATE(H)
= C
GATE(L)
< 10 nF, Note 4
Measure GATE(L) or GATE(H)
0.5 nF < C
GATE(H)
= C
GATE(L)
< 10 nF, Note 4
Resistance to GND. Note 4
−
−
40
40
−
V
CC
−
0.5
−
20
40
40
60
60
250
V
CC
0
50
80
80
105
105
−
−
0.5
115
ns
ns
ns
ns
ns
V
V
kW
ELECTRICAL CHARACTERISTICS
(0°C < T
J
< 125°C, 9.0 V < V
CC
< 20 V, C
GATE(H)
= C
GATE(L)
= 3.3 nF,
Test Conditions
Min
Typ
Max
Unit
General Electrical Specifications
V
CC
Supply Current
Start Threshold
Stop Threshold
Hysteresis
COMP = 0 V (No Switching)
GATE(H) Switching, COMP Charging
GATE(H) Not Switching, COMP Discharging
Start − Stop
−
8.0
7.0
0.75
9.0
8.5
7.5
1.0
12
9.0
8.0
1.25
mA
V
V
V
3. Characteristics at temperature extremes are guaranteed via correlation using quality statistical control methods.
4. Guaranteed by design. Not tested in production.
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