CY7C144E
8K × 8 Dual-Port Static RAM
with SEM, INT, BUSY
8K × 8 Dual-Port Static RAM with SEM, INT, BUSY
Features
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Functional Description
The CY7C144E is a high speed CMOS 8K × 8 dual port static
RAM. Various arbitration schemes are included on the
CY7C144E to handle situations when multiple processors
access the same piece of data. Two ports are provided permitting
independent, asynchronous access for reads and writes to any
location in memory. The CY7C144E can be used as a
standalone 64-Kbit dual-port static RAM or multiple devices can
be combined in order to function as a 16-bit or wider
master/slave dual-port static RAM. An M/S pin is provided for
implementing 16-bit or wider memory applications without the
need for separate master and slave devices or additional
discrete
logic.
Application
areas
include
interprocessor/multiprocessor designs, communications status
buffering, and dual-port video / graphics memory.
Each port has independent control pins: chip enable (CE), read
or write enable (R/W), and output enable (OE). Two flags, BUSY
and INT, are provided on each port. BUSY signals that the port
is trying to access the same location currently being accessed
by the other port. The interrupt flag (INT) permits communication
between ports or systems by means of a mail box. The
semaphores are used to pass a flag, or token, from one port to
the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power-down feature is controlled independently on
each port by a chip enable (CE) pin or SEM pin.
For a complete list of related documentation, click
here.
True dual-ported memory cells that enable simultaneous reads
of the same memory location
8K × 8 organization (CY7C144E)
0.35-micron CMOS for optimum speed and power
High-speed access: 15 ns
Low operating power: I
CC
= 180 mA (typical),
standby ISB3 = 0.05 mA (typical)
Fully asynchronous operation
Automatic power-down
TTL compatible
Master / slave select pin enables bus width expansion to 16-bits
or more
Busy arbitration scheme provided
Semaphores included to permit software handshaking
between ports
INT flag for port-to-port communication
Available in 68-pin PLCC and 64-pin TQFP
Pb-free packages available
Logic Block Diagram
R/W
L
CE
L
OE
L
R/W
R
CE
R
OE
R
I/O
7L
I/O
0L
BUSY
L
[1, 2]
A
12L
A
0L
ADDRESS
DECODER
I/O
CONTROL
I/O
CONTROL
I/O
7R
I/O
0R
BUSY
R
[1, 2]
A
12R
MEMORY
ARRAY
ADDRESS
DECODER
A
0R
CE
L
OE
L
R/W
L
SEM
L
INT
L
[2]
INTERRUPT
SEMAPHORE
ARBITRATION
CE
R
OE
R
R/W
R
SEM
R
INT
R
[2]
M/S
Notes
1. BUSY is an output in master mode and an input in slave mode.
2. Interrupt: push-pull output and requires no pull-up resistor.
Cypress Semiconductor Corporation
Document Number: 001-63982 Rev. *E
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 5, 2018
CY7C144E
Contents
Selection Guide ................................................................ 3
Pin Configuration ............................................................. 3
Pin Definitions .................................................................. 4
Architecture ...................................................................... 4
Functional Overview ........................................................ 5
Write Operation ........................................................... 5
Read Operation ........................................................... 5
Interrupts ..................................................................... 5
Busy ............................................................................ 5
Master/Slave ............................................................... 6
Semaphore Operation ................................................. 6
Maximum Ratings ............................................................. 7
Operating Range ............................................................... 7
Electrical Characteristics ................................................. 7
Capacitance ...................................................................... 8
AC Test Loads and Waveforms ....................................... 8
Switching Characteristics ................................................ 9
Switching Waveforms .................................................... 11
Typical DC and AC Characteristics .............................. 17
Ordering Information ...................................................... 18
Ordering Code Definitions ......................................... 18
Package Diagrams .......................................................... 19
Acronyms ........................................................................ 21
Document Conventions ................................................. 21
Units of Measure ....................................................... 21
Document History Page ................................................. 22
Sales, Solutions, and Legal Information ...................... 23
Worldwide Sales and Design Support ....................... 23
Products .................................................................... 23
PSoC® Solutions ...................................................... 23
Cypress Developer Community ................................. 23
Technical Support ..................................................... 23
Document Number: 001-63982 Rev. *E
Page 2 of 23
CY7C144E
Selection Guide
Description
Maximum access time
Typical operating current
Typical Standby Current for ISB1
(both ports TTL level)
Typical Standby Current for ISB3
(both ports CMOS level)
7C144E-15
15
190
50
0.05
7C144E-25
25
180
45
0.05
7C144E-55
55
180
45
0.05
Unit
ns
mA
mA
mA
Pin Configuration
Figure 1. 68-pin PLCC pinout (Top View)
IO 1 L
IO 0 L
NC
[3]
OE L
R/WL
SEM
L
CEL
NC
NC
VCC
A
12 L
A 1L
1
A 0L
1
Figure 2. 64-pin TQFP pinout (Top View)
S E M
L
R/ W
L
1L
0L
O E
L
A
1 1L
A
12L
A
1 0L
CE
L
V
CC
A
9 L
A
8 L
A
7 L
A
6 L
50
IO
64
63
62
61
60
58
57
56
55
54
53
52
51
IO
2L
IO
3L
IO
4L
IO
5L
GND
IO
6L
IO
7L
V
CC
GND
IO
0R
IO
1R
IO
2R
V
CC
IO
3R
IO
4R
IO
5R
IO
6R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43
R/WR
SEM
R
CER
NC
NC
GND
A12R
A11R
A10R
A9R
IO 7R
NC
OE
R
A8R
A7R
A6R
A5R
CY7C144E
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
IO
2L
IO
3L
IO
4L
IO
5L
GND
IO
6L
IO
7L
V
CC
GND
IO
0R
IO
1R
IO
2R
V
CC
IO
3R
IO
4R
IO
5R
59
49
9 8 7 6
5 4 3 2 1 68 67 66 65 64 63 62 61
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A9L
A8L
A7L
A6L
IO
A
5 L
NC
48
47
46
45
44
43
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
CY7C144E
42
41
40
39
38
37
36
35
34
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
O E
R
R/ W
R
SE M
R
CE
R
6R
7R
A
9 R
A
8 R
A
7 R
A
6 R
A
1 1 R
IO
Note
3. This pin is NC.
Document Number: 001-63982 Rev. *E
IO
G ND
A
1 2 R
A
1 0 R
A
5 R
NC
32
33
Page 3 of 23
CY7C144E
Pin Definitions
Left Port
I/O
0L-7L
A
0L-12L
CE
L
OE
L
R/W
L
SEM
L
INT
L
BUSY
L
M/S
V
CC
GND
Right Port
I/O
0R-7R
A
0R-12R
CE
R
OE
R
R/W
R
SEM
R
INT
R
BUSY
R
Data bus I/O
Address lines
Chip enable
Output enable
Read / write enable
Semaphore enable. When asserted LOW, allows access to eight semaphores. The three least significant
bits of the address lines will determine which semaphore to write or read. The I/O
0
pin is used when writing
to a semaphore. Semaphores are requested by writing a 0 into the respective location.
Interrupt Flag. INT
L
is set when right port writes location 1FFE and is cleared when left port reads location
1FFE. INT
R
is set when left port writes location 1FFF
[4]
and is cleared when right port reads location 1FFF
[4]
.
Busy flag
Master or slave select
Power
Ground
for port-to-port communication. Two semaphore (SEM) control
pins are used for allocating shared resources. With the M/S pin,
the CY7C144E can function as a Master (BUSY pins are outputs)
or as a slave (BUSY pins are inputs). The CY7C144E has an
automatic power-down feature controlled by CE. Each port is
provided with its own output enable control (OE), which allows
data to be read from the device.
Description
Architecture
The CY7C144E consists of a an array of 8K words of 8 bits each
of dual-port RAM cells, I/O, address lines, and control signals
(CE, OE, R/W). These control pins permit independent access
for reads/writes to any location in memory. To handle
simultaneous writes or reads to the same location, a BUSY pin
is provided on each port. Two interrupt (INT) pins can be used
Note
4. 8K x 8 (CY7C144E): 1FFE(left port) and 1FFF(right port).
Document Number: 001-63982 Rev. *E
Page 4 of 23
CY7C144E
Functional Overview
Write Operation
Data must be set up for a duration of t
SD
before the rising edge
of R / W to guarantee a valid write. A write operation is controlled
by either the OE pin (see
Figure 7 on page 12)
or the R/W pin
(see
Figure 8 on page 12).
Data can be written to the device
t
HZOE
after the OE is deasserted or t
HZWE
after the falling edge
of R/W. Required inputs for non-contention operations are
summarized in
Table 1.
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must be met before the data is read on the output; otherwise the
data read is not deterministic. Data will be valid on the port t
DDD
after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE and
CE pins. Data will be available t
ACE
after CE or t
DOE
after OE are
asserted. If the user of the CY7C144E wishes to access a
semaphore flag, then the SEM pin must be asserted instead of
the CE pin.
Table 1. Non-Contending Read/Write
Inputs
CE
H
H
X
H
L
L
L
H
L
X
R/W
X
H
X
OE
X
L
H
X
L
X
X
SEM
H
L
X
L
H
H
L
Outputs
I/O
07
High Z
Data out
High Z
Data in
Data out
Data in
Power-down
Read data in semaphore
I/O lines disabled
Write to semaphore
Read
Write
Illegal condition
(INT
L
) is accomplished when the right port writes to location
1FFE. This flag is cleared when the left port reads the specified
location 1FFE. The message at 1FFF or 1FFE is user-defined.
See
Table 2
for input requirements for INT. INT
R
and INT
L
are
push-pull outputs and do not require pull-up resistors to operate.
Operation
Interrupts
The interrupt flag (INT) permits communications between
ports.When the left port writes to location 1FFF, the right port’s
interrupt flag (INT
R
) is set. This flag is cleared when the right port
reads that same location. Setting the left port’s interrupt flag
Table 2. Interrupt Operation Example (assumes BUSY
L
= BUSY
R
= HIGH)
Function
Set left INT
Reset left INT
Set right INT
Reset right INT
Left Port
R/W
X
X
L
X
CE
X
L
L
X
OE
X
L
X
X
A
012
(CY7C144E)
X
1FFE
1FFF
X
INT
L
H
X
X
R/W
L
X
X
X
CE
L
L
X
L
Right Port
OE
X
L
X
L
A
012
(CY7C144E)
1FFE
X
X
1FFF
INT
X
X
L
H
Busy
The CY7C144E provides on-chip arbitration to alleviate
simultaneous memory location access (contention). If both ports’
CEs are asserted and an address match occurs within t
PS
of
each other the Busy logic determines which port has access. If
t
PS
is violated, one port will definitely gain permission to the
location, but it is not guaranteed which one. BUSY will be
asserted t
BLA
after an address match or t
BLC
after CE is taken
LOW. BUSY
L
and BUSY
R
in master mode are push-pull outputs
and do not require pull-up resistors to operate.
Document Number: 001-63982 Rev. *E
Page 5 of 23
PCB设计
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
