74LVC544A
Octal D-type registered transceiver; inverting; 3-state
Rev. 4 — 18 December 2012
Product data sheet
1. General description
The 74LVC544A is an octal registered inverting transceiver containing two sets of D-type
latches for temporary storage of the data flow in either direction. Separate latch enable
inputs (LEAB and LEBA) and output enable inputs (OEAB and OEBA) are provided for
each register to permit independent control of input and output in either direction of the
data flow.
The 74LVC544A contains eight D-type latches, with separate inputs and controls for each
set. For data flow from pins A to B, for example, the A to B enable input (pin EAB) must be
LOW in order to enter data from pins A0 to A7 or take data from pins B0 to B7. With
pin EAB LOW, a LOW signal on the A to B latch enable input (pin LEAB) makes the A to B
latches transparent; a subsequent LOW-to-HIGH transition on pin LEAB puts the A data
into the latches where it is stored and the B outputs no longer change with the A inputs.
With pins EAB and OEAB both LOW, the 3-state B output buffers are active and display
the data present at the outputs of the A latches.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low-power consumption
Direct interface with TTL levels
8-bit octal transceiver with D-type latch
Back-to-back registers for storage
Separate controls for data flow in each direction
Supports partial power-down applications; inputs/outputs are high-impedance when
V
CC
= 0 V
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74LVC544A
Octal D-type registered transceiver; inverting; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74LVC544AD
74LVC544ADB
74LVC544APW
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
SO24
SSOP24
TSSOP24
Description
plastic small outline package; 24 leads;
body width 7.5 mm
plastic shrink small outline package; 24 leads;
body width 5.3 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
Version
SOT137-1
SOT340-1
SOT355-1
Type number
4. Functional diagram
2
23
1
13
11
14
3
4
5
6
7
8
9
10
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
22
21
20
19
18
17
16
15
5
6
7
8
11
23
14
1
EAB
EBA
LEAB
LEBA
001aaa782
1EN3
G1
1C5
2EN4
G2
2C6
3
3
6D
5D
4
22
4
21
20
19
18
17
16
15
2
13
OEBA
OEAB
9
10
001aaa783
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74LVC544A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 18 December 2012
2 of 19
NXP Semiconductors
74LVC544A
Octal D-type registered transceiver; inverting; 3-state
OEBA
EBA
LEBA
OEAB
EAB
LEAB
LE
D
An
LE
Bn
D
8 identical
channels
001aaa784
To 7 other channels
Fig 3.
Logic diagram
5. Pinning information
5.1 Pinning
LEBA
OEBA
A0
A1
A2
A3
A4
A5
A6
1
2
3
4
5
6
7
8
9
24 V
CC
23 EBA
22 B0
21 B1
20 B2
19 B3
18 B4
17 B5
16 B6
15 B7
14 LEAB
13 OEAB
001aaa780
544
A7 10
EAB 11
GND 12
Fig 4.
Pin configuration for SO24 and (T)SSOP24
74LVC544A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 18 December 2012
3 of 19
NXP Semiconductors
74LVC544A
Octal D-type registered transceiver; inverting; 3-state
5.2 Pin description
Table 2.
Symbol
LEBA
OEBA
A0
A1
A2
A3
A4
A5
A6
A7
EAB
GND
OEAB
LEAB
B7
B6
B5
B4
B3
B2
B1
B0
EBA
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Description
B to A latch enable input (active LOW)
B to A output enable input (active LOW)
A data input or output
A data input or output
A data input or output
A data input or output
A data input or output
A data input or output
A data input or output
A data input or output
A to B enable input (active LOW)
ground (0 V)
A to B output enable input (active LOW)
A to B latch enable input (active LOW)
B data output or input
B data output or input
B data output or input
B data output or input
B data output or input
B data output or input
B data output or input
B data output or input
B to A enable input (active LOW)
supply voltage
74LVC544A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 18 December 2012
4 of 19
NXP Semiconductors
74LVC544A
Octal D-type registered transceiver; inverting; 3-state
6. Functional description
Table 3.
Function table
[1]
Input
OEAB, OEBA EAB, EBA
Disabled
Disabled plus latch
Latch plus display
Transparent
Hold (do nothing)
[1]
Operating mode
Output
LEAB, LEBA
X
X
L
L
L
L
H
An, Bn
X
X
h
l
h
l
H
L
X
Bn, An
Z
Z
Z
Z
L
H
L
H
NC
X
H
L
L
L
L
L
H
X
L
L
L
L
L
L
L
XX = AB for A to B direction and BA for B to A direction
H = HIGH voltage level
L = LOW voltage level
h = HIGH state must be present one set-up time before the LOW-to-HIGH transition of LEAB, LEBA, EAB and EBA
l = LOW state must be present one set-up time before the LOW-to-HIGH transition of LEAB, LEBA, EAB and EBA
X = don’t care
= LOW to HIGH level transition
NC = no change
Z = high-impedance OFF-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
-
[2]
[2]
Max
+6.5
-
+6.5
50
V
CC
+ 0.5
+6.5
50
100
-
+150
500
Unit
V
mA
V
mA
V
V
mA
mA
mA
C
mW
V
O
> V
CC
or V
O
< 0 V
output HIGH or LOW state
output 3-state
V
O
= 0 V to V
CC
0.5
0.5
-
-
100
65
T
amb
=
40 C
to +125
C
[3]
-
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
For SO24 packages: above 70
C
the value of P
tot
derates linearly with 8 mW/K.
For (T)SSOP24 packages: above 60
C
the value of P
tot
derates linearly with 5.5 mW/K.
74LVC544A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 18 December 2012
5 of 19
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