74AHC3GU04
Triple unbuffered inverter
Rev. 5 — 8 May 2013
Product data sheet
1. General description
The 74AHC3GU04 is a high-speed Si-gate CMOS device. This device provides three
inverter gates with unbuffered outputs.
2. Features and benefits
Symmetrical output impedance
High noise immunity
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101D exceeds 1000 V
Low power dissipation
Balanced propagation delays
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AHC3GU04DP
74AHC3GU04DC
74AHC3GU04GD
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
TSSOP8
VSSOP8
XSON8
Description
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
Version
SOT505-2
Type number
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; body 3
2
0.5 mm
NXP Semiconductors
74AHC3GU04
Triple unbuffered inverter
4. Marking
Table 2.
Marking codes
Marking code
[1]
AU4
AU4
AU4
Type number
74AHC3GU04DP
74AHC3GU04DC
74AHC3GU04GD
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1
1
7
1
1A
1Y
7
3
1
5
3
2A
2Y
5
1
6
3A
3Y
2
6
2
A
Y
mna045
mna720
mna721
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram (one gate)
6. Pinning information
6.1 Pinning
74AHC3GU04
1A
1
2
3
4
8
7
6
5
V
CC
1Y
3A
2Y
74AHC3GU04
1A
3Y
2A
GND
1
2
3
4
001aaj517
3Y
8
7
6
5
V
CC
1Y
3A
2Y
2A
GND
001aaj518
Transparent top view
Fig 4.
Pin configuration SOT505-2 (TSSOP8) and
SOT765-1 (VSSOP8)
Fig 5.
Pin configuration SOT996-2 (XSON8)
74AHC3GU04
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 8 May 2013
2 of 16
NXP Semiconductors
74AHC3GU04
Triple unbuffered inverter
6.2 Pin description
Table 3.
Symbol
1A, 2A, 3A
GND
1Y, 2Y, 3Y
V
CC
Pin description
Pin
1, 3, 6
4
7, 5, 2
8
Description
data input
ground (0 V)
data output
supply voltage
7. Functional description
Table 4.
Function table
H = HIGH voltage level; L = LOW voltage level
Input
A
L
H
Output
Y
H
L
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
Min
0.5
0.5
Max
+7.0
+7.0
-
20
25
75
-
+150
250
Unit
V
V
mA
mA
mA
mA
mA
C
mW
V
I
<
0.5
V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
0.5
V < V
O
< V
CC
+ 0.5 V
[1]
[1]
20
-
-
-
75
65
T
amb
=
40 C
to +125
C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For TSSOP8 package: above 55
C
the value of P
tot
derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110
C
the value of P
tot
derates linearly with 8 mW/K.
For XSON8 package: above 45
C
the value of P
tot
derates linearly with 2.4 mW/K.
74AHC3GU04
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 8 May 2013
3 of 16
NXP Semiconductors
74AHC3GU04
Triple unbuffered inverter
9. Recommended operating conditions
Table 6.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
V
I
V
O
T
amb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 3.3 V
0.3 V
V
CC
= 5.0 V
0.5 V
Conditions
Min
2.0
0
0
40
-
-
Typ
5.0
-
-
+25
-
-
Max
5.5
5.5
V
CC
+125
100
20
Unit
V
V
V
C
ns/V
ns/V
10. Static characteristics
Table 7.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol
V
IH
Parameter
HIGH-level
input voltage
Conditions
Min
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 5.5 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 5.5 V
V
OH
HIGH-level
V
I
= V
IH
or V
IL
output voltage
I
O
=
50 A;
V
CC
= 2.0 V
I
O
=
50 A;
V
CC
= 3.0 V
I
O
=
50 A;
V
CC
= 4.5 V
1.7
2.4
4.4
-
-
-
1.9
2.9
4.4
-
-
-
-
-
-
2.0
3.0
4.5
-
-
0
0
0
-
-
- -
- -
- 3.0
25
C
Typ
Max
-
-
-
0.3
0.6
1.1
-
-
-
-
-
0.1
0.1
0.1
0.36
0.36
0.1
1.0
10
40 C
to +85
C
Min
1.7
2.4
4.4
-
-
-
1.9
2.9
4.4
2.48
3.8
-
-
-
-
-
-
-
-
-
-
-
0.3
0.6
1.1
-
-
-
-
-
0.1
0.1
0.1
0.44
0.44
1.0
10
10
Max
40 C
to +125
C
Unit
Min
1.7
2.4
4.4
-
-
-
1.9
2.9
4.4
2.40
3.70
-
-
-
-
-
-
-
-
-
-
-
0.3
0.6
1.1
-
-
-
-
-
0.1
0.1
0.1
0.55
0.55
2.0
40
10
Max
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
A
A
pF
I
O
=
4.0
mA; V
CC
= 3.0 V 2.58
I
O
=
8.0
mA; V
CC
= 4.5 V 3.94
V
OL
LOW-level
V
I
= V
IH
or V
IL
output voltage
I
O
= 50
A;
V
CC
= 2.0 V
I
O
= 50
A;
V
CC
= 3.0 V
I
O
= 50
A;
V
CC
= 4.5 V
I
O
= 4.0 mA; V
CC
= 3.0 V
I
O
= 8.0 mA; V
CC
= 4.5 V
I
I
I
CC
C
I
input leakage
current
V
I
= 5.5 V or GND;
V
CC
= 0 V to 5.5 V
-
-
-
-
-
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
input
capacitance
74AHC3GU04
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 8 May 2013
4 of 16
NXP Semiconductors
74AHC3GU04
Triple unbuffered inverter
11. Dynamic characteristics
Table 8.
Dynamic characteristics
GND = 0 V; For test circuit see
Figure 7.
Symbol
t
pd
Parameter
propagation
delay
Conditions
Min
nA to nY; see
Figure 6
V
CC
= 3.0 V to 3.6 V
C
L
= 15 pF
C
L
= 50 pF
V
CC
= 4.5 V to 5.5 V
C
L
= 15 pF
C
L
= 50 pF
C
PD
power
dissipation
capacitance
per buffer;
V
I
= GND to V
CC
[4]
[3]
[1]
[2]
25
C
Typ
Max
40 C
to +85
C 40 C
to +125
C
Unit
Min
Max
Min
Max
-
-
-
-
-
3.0
4.3
2.5
3.5
4
7.1
10.6
5.5
7.0
-
1.0
1.0
1.0
1.0
-
8.5
12.0
6.0
8.0
-
1.0
1.0
1.0
1.0
-
10.0
13.5
7.0
9.0
-
ns
ns
ns
ns
pF
[1]
[2]
[3]
[4]
t
pd
is the same as t
PLH
and t
PHL
.
Typical values are measured at V
CC
= 3.3 V.
Typical values are measured at V
CC
= 5.0 V.
C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC2
f
i
N +
(C
L
V
CC2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC2
f
o
) = sum of the outputs.
12. Waveforms
V
I
nA input
GND
t
PHL
V
OH
nY output
V
OL
V
M
V
M
mna344
V
M
V
M
t
PLH
Fig 6.
Table 9.
Type
The input (nA) to output (nY) propagation delays.
Measurement points
Input
V
M
0.5V
CC
Output
V
M
0.5V
CC
74AHC3GU04
74AHC3GU04
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 8 May 2013
5 of 16
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