6N135,6N136
TOSHIBA Photocoupler
GaAℓAs Ired & Photo IC
6N135, 6N136
Digital Logic Isolation
Line Receiver
Power Supply Control
Switching Power Supply
Transistor Inverter
Unit: mm
The TOSHIBA 6N135 and 6N136 consists of a high emitting diode and a
one chip photo diode−transistor.
Each unit is 8−lead DIP package.
•
•
•
•
•
Isolation voltage: 2500 V
rms
(min)
High speed: t
pHL
, t
pLH
= 0.5
μs
(typ.) (R
L
= 1.9kΩ)
TTL compatible
If base pin is open, output signal will be noisy by environmental
condition. For this base, TLP550 is suitable
UL recognized: UL1577, file no. E67349
TOSHIBA
11−10C4
Weight: 0.54 g (typ.)
Pin Configurations
1
2
3
4
8
7
6
5
1 : N.C.
2 : ANODE
3 : CATHODE
4 : N.C.
5 : EMITTER
6 : COLLECTOR
7 : BASE, ANODE
8 : CATHODE
I
CC
I
F
V
F
2
3
I
B
I
O
8 V
CC
7 V
B
6 V
O
5 GND
Start of commercial production
1982/10
1
2014-09-22
6N135,6N136
Absolute Maximum Ratings
(Ta = 25°C)
Characteristic
Forward current
Pulse forward current
LED
Total pulse forward current
Reverse voltage
Diode power dissipation
Output current
Peak output current
Detector
Emitter−base reverse voltage (pin 5−7)
Supply voltage
Output voltage
Base current (pin 7)
Output power dissipation
Operating temperature range
Storage temperature range
Lead solder temperature (10s)
Isolation voltage
(Note 6)
(Note 7)
(Note 5)
(Note 4)
(Note 1)
(Note 2)
(Note 3)
Symbol
I
F
I
FP
I
FPT
V
R
P
D
I
O
I
OP
V
EB
V
CC
V
O
I
B
P
o
T
opr
T
stg
T
sol
BV
S
Rating
25
50
1
5
45
8
16
5
−0.5
to 15
−0.5
to 15
5
100
−55
to 100
−55
to 125
260
2500
Unit
mA
mA
A
V
mW
mA
mA
V
V
V
mA
mW
°C
°C
°C
V
rms
Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if
the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc.).
(Note 1)
(Note 2)
(Note 3)
(Note 4)
(Note 5)
(Note 6)
(Note 7)
Derate 0.8 mA above 70°C.
50% duty cycle, 1ms pulse width.
Derate 1.6 mA / °C above 70°C.
Pulse width 1μs, 300pps.
Derate 0.9 mW / °C above 70°C.
Derate 2 mW / °C above 70°C.
Soldering portion of lead: Up to 2mm from the body of the device.
R.H.
≤
60%, AC, 1minute
2
2014-09-22
6N135,6N136
Electrical Characteristics
Over Recommended Temperature
(Ta = 0°C~70°C unless otherwise noted)
Characteristic
6N135
Current transfer ratio
6N136
6N135
6N136
6N135
Logic low output voltage
6N136
V
OL
Symbol
CTR
Test Condition
I
F
= 16mA, V
O
= 0.4V
V
CC
= 4.5V, Ta = 25°C
I
F
= 16mA, V
O
= 0.5V
V
CC
= 4.5V
I
F
= 16mA, I
O
= 1.1mA
V
CC
= 4.5V
I
F
= 16mA, I
O
= 2.4mA
V
CC
= 4.5V
I
F
= 0mA, V
O
= V
CC
= 5.5V
Ta = 25°C
I
F
= 0mA, V
O
= V
CC
= 15V
Ta = 25°C
I
F
= 0 mA, V
O
= V
CC
= 15V
I
F
= 16mA, V
O
= open
V
CC
= 15V
I
F
= 0mA, V
O
= open
V
CC
= 15V, Ta = 25°C
I
F
= 0mA, V
O
= open
V
CC
= 15V
I
F
= 16mA, Ta = 25°C
I
F
= 16mA
I
R
= 10μA, Ta = 25°C
f = 1MHz, V
F
= 0
V
I−O
= 500V
R.H.
≤
60%
f = 1MHz
V
O
= 5V, I
O
= 3mA
(Note 9)
(Note 9)
Min
7
(Note 8)
19
5
(Note 1)
15
―
―
―
―
―
―
―
―
―
―
5
―
―
―
―
(**)Typ.
18
24
13
21
0.1
0.1
3
0.1
―
40
0.01
―
1.65
−1.9
―
60
10
12
Max
―
―
―
―
0.4
0.4
500
1
50
―
1
2
1.7
―
―
―
―
―
―
Unit
%
%
%
%
V
V
nA
μA
μA
μA
μA
μA
V
mV / °C
V
pF
Ω
pF
―
CTR
Logic high output current
I
OH
I
OH
Logic low supply current
I
CCL
I
CCH
Logic high supply current
I
CCH
Input forward voltage
Temperature coefficient of
forward voltage
Input reverse breakdown voltage
Input capacitance
Resistance (input−output)
Capacitance (input−output)
Transistor DC current gain
V
F
∆V
F
/
∆Ta
BV
R
C
IN
R
I−O
C
I−O
h
FE
0.6
80
(**) All typical values are at Ta = 25°C
3
2014-09-22
6N135,6N136
Switching Specifications
Characteristic
Propagation delay time
to logic low at output
Propagation delay time
to logic high at output
6N135
6N136
6N135
6N136
6N135
CM
H
6N136
2
(unless otherwise specified. Ta = 25°C, V
CC
= 5V, I
F
= 16mA)
Symbol
t
pHL
Test
Circuit
1
Test Condition
R
L
= 4.1kΩ
R
L
= 1.9kΩ
R
L
= 4.1kΩ
R
L
= 1.9kΩ
I
F
= 0mA
V
CM
= 10V
p−p
R
L
= 4.1kΩ
I
F
= 0mA
V
CM
= 10V
p−p
R
L
= 1.9kΩ
V
CM
= 10V
p−p
R
L
= 4.1kΩ
I
F
= 16mA
V
CM
= 10V
p−p
R
L
= 1.9kΩ
I
F
= 16mA
R
L
= 100Ω
Min
―
―
―
―
―
Typ.
0.2
0.2
1.0
0.5
1000
Max
1.5
0.8
1.5
0.8
―
Unit
μs
μs
μs
μs
V /
μs
t
pLH
1
Common mode
transient immunity
at logic high level
output
(Note 10)
―
1000
―
V /
μs
Common mode
transient immunity
at logic low level
output
(Note 10)
Bandwidth
6N135
CM
L
6N136
(Note 11)
BW
―
2
―
−1000
―
V /
μs
―
―
−1000
2
―
―
V /
μs
MHz
(Note 8)
(Note 9)
DC current transfer ratio is defined as the ratio of output collector current, I
O
, to the forward LED input current,
I
F
, times 100%.
Device considered a two−terminal device: Pins 1, 2, 3 and 4 shorted together and pins 5, 6, 7 and 8 shorted
together.
(Note 10) Common mode transient immunity in logic high level is the maximum tolerable (positive) dV
CM
/ dt on the
leading edge of the common mode pulse, V
CM
, to assure that the output will remain in a logic high state (i.e.,
V
O
> 2.0V).
Common mode transient immunity in logic low level is the maximum tolerable (negative) dV
CM
/ dt on the
trailing edge of the common mode pulse signal, V
CM
, to assure that the output will remain in a logic low state
(i.e., V
O
< 0.8V).
(Note 11) The frequency at which the AC output voltage is 3dB below the low frequency asymptote.
4
2014-09-22
6N135,6N136
Test Circuit 1.
PULSE GEN.
Z
o
= 50Ω
t
f
= 5ns
10% DUTY
CYCLE
I
F
MONITOR
I
F
I
F
0
V
O
1.5V
1.5V
V
OL
5V
1
2
3
8
7
6
5
R
L
5V
t
pHL
t
pLH
100Ω
4
V
O
(*)
C
L
(*) C
L
is approximately 15
P
F which includes probe and stray
wiring capacitance.
Test Circuit 2.
I
F
10V
V
CM
0V
V
O
SWITCH AT A : I
F
= 0mA
V
O
SWITCH AT B
: I
F
= 16mA
V
OL
t
r,
t
f
= 8ns
10%
90%
90%
10%
t
f
t
r
5V
A
B
V
FF
1
2
3
4
V
CM
PULSE GEN.
8
7
6
5
R
L
5V
V
O
5
2014-09-22
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