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VSC7186: 产品描述Quad Transceiver for Gigabit Ethernet; 文件大小221KB，共16页; 制造商Vitesse Semiconductor Corporation; 官网地址http://www.vitesse.com/

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VSC7186概述

Quad Transceiver for Gigabit Ethernet

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VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC7186

Features

• Four Complete Transceiver Functions in One IC

• Full Gigabit Ethernet (IEEE 802.3z) Compliance

• Pin-Compatible With Agilent HDMP-1686A

• 5-Volt Tolerant TTL Inputs

• Uses Reference Clock to Latch Tx Data

• 1/10

or 1/20

Baud Rate Recovered Clocks

• Common Local Loopback Control

Quad Transceiver

for Gigabit Ethernet

• Single Comma Detect Enable

• Cable Equalization in Receivers

• Automatic Lock-to-Reference

• JTAG Access Port

• 2kV ESD Protection on All Pins

• 3.3V Power Supply, 2.67 W Max Dissipation

• 208 pin, 23 mm BGA Packaging

General Description

The VSC7186 is a Quad Gigabit Ethernet Transceiver IC. Each of the four transmitters has a 10-bit wide

bus, running at 125 MHz, which accepts 8b/10b encoded transmit characters and serializes the data onto high

speed differential outputs at rates between 1.05 and 1.36 Gb/s. The transmit data must be synchronous to the

reference clock. Each receiver samples serial receive data, recovers the clock and data, deserializes it into 10-bit

receive characters, outputs a recovered clock and detects “Comma” characters. The VSC7186 contains on-chip

PLL circuitry for synthesis of the baud-rate transmit clock and extraction of the clocks from the received serial

streams.

VSC7186 Block Diagram (1 of 4 Channels)

RXi(0:9)

Serial to

Q Parallel D

Clock

Recovery

÷10

Unit

SI+

SI-

RCM

RCi1

RCi0

SYNi

SYNC

LOOP

Comma

Detect

SEL

÷10/

÷20

TXi(0:9)

Parallel

to Serial

SO+

SO-

RFC1

CAP0

CAP1

Clock

Multiply

Unit

x10

G52306-0, Rev. 2.0

3/27/00



VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

Page

VITESSE

SEMICONDUCTOR CORPORATION

Quad Transceiver

for Gigabit Ethernet

Advance Product Information

VSC7186

Functional Description

Notation

In this document, each of the four channels are identified as Channel 0, 1, 2 or 3. When discussing a signal

on any specific channel, the signal will have the Channel number embedded in the name, i.e. “T3(0:9)”. When

referring to the common behavior of a signal which is used on each of the four channels, the notation “i” is used.

Differential signals, i.e. SOi+ and SOi-, may be referred to as a single signal, i.e. SOi, by dropping reference to

the “+” and “-”.

Clock Synthesizer

The VSC7186 Clock Multiplier Unit (CMU) multiplies the reference frequency provided on the RFC1

input by 10 to achieve a baud rate clock between 1.05 and 1.36 GHz. The RFC1 input is TTL. The on-chip PLL

uses a single external 0.1uF capacitor, connected between CAP0 and CAP1, to control the Loop Filter. This

capacitor should be a multilayer ceramic dielectric, or better, with at least a 5V working voltage rating and a

good temperature coefficient, i.e., NPO is preferred but X7R may be acceptable. These capacitors are used to

minimize the impact of common mode noise on the Clock Multiplier Unit, especially power supply noise.

Higher value capacitors provide better robustness in systems. NPO is preferred because if an X7R capacitor is

used, the power supply noise sensitivity will vary with temperature.

For best noise immunity, the designer may use a three capacitor circuit with one differential capacitor

between CAP0 and CAP1, C1, a capacitor from CAP0 to ground, C2, and a capacitor from CAP1 to ground,

C3. Larger values are better but 0.1uF is adequate. However, if the designer cannot use a three capacitor circuit,

a single differential capacitor, C1, is adequate. These components should be isolated from noisy traces.

Figure 1: Loop Filter Capacitors (Best Circuit)

CAP0

VSC7186

CAP1

C1=C2=C3= >0.1uF

MultiLayer Ceramic

Surface Mount

NPO (Prefered) or X7R

5V Working Voltage Rating

Serializer

The VSC7186 accepts TTL input data as four parallel 10 bit characters on the Ti(0:9) buses which are

latched into the input registers on the rising edge of RFC1. The 10-bit parallel transmission character will be

serialized and transmitted on the SOi+/- PECL differential outputs at the baud rate with bit Ti0 (bit a) transmit-

ted first. User data should be encoded using 8b/10b or an equivalent code. The mapping to 10b encoded bit

nomenclature and transmission order is illustrated below, along with the recognized comma pattern.

Page 2



VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52306-0, Rev. 2.0

3/27/00

VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC7186

Table 1: Transmission Order and Mapping of a 10b Character

Quad Transceiver

for Gigabit Ethernet

Data Bit

10B Bit Position

Comma Character

Clock Recovery

The VSC7186 accepts differential high speed serial input from the selected source (either the PECL SIi+/-

pins or the internal SOi+/- data), extracts the clock and retimes the data. Equalizers are included in the receiver

to open the data eye and compensate for Intersymbol Interference (ISI) which may be present in the incoming

data. The serial bit stream should be encoded so as to provide DC balance and limited run length by an 8b/10b

encoding scheme. The digital Clock Recovery Unit (CRU) is completely monolithic and requires no external

components. For proper operation, the baud rate of the data stream to be recovered should be within +200 ppm

of ten times the REF frequency. For example, Gigabit Ethernet systems use 125 MHz oscillators with a +/-

100ppm accuracy resulting in +/-200 ppm between VSC7186 pairs.

Deserializer

The recovered serial bit stream is converted into a 10-bit parallel output character. The VSC7186 provides

complementary TTL recovered clocks, RCi0 and RCi1, at one-twentieth of the serial baud rate if RCM=LOW,

or a single clock at one-tenth the serial baud rate, on RCi1 only, if RCM=HIGH. The clocks are generated by

dividing down the high-speed recovered clock which is phase locked to the serial data. The serial data is

retimed, deserialized and output on Ri(0:9).

If serial input data is not present, or does not meet the required baud rate, the VSC7186 will continue to

produce a recovered clock so that downstream logic may continue to function. The RCi0/RCi1 output frequency

under these circumstances will differ from its expected frequency by no more than +1%.

Word Alignment

The VSC7186 provides 7-bit comma character recognition and data word alignment. Word synchronization

is enabled on all channels by asserting SYNC HIGH. When synchronization is enabled, the receiver examines

the recovered serial data for the presence of the “Comma” pattern. This pattern is “0011111XXX”, where the

leading zero corresponds to the first bit received. The comma sequence is not contained in any normal 8b/10b

coded data character or pair of adjacent characters. It occurs only within special characters, known as K28.1,

K28.5 and K28.7, which are defined for synchronization purposes. Improper comma alignment is defined as

any of the following conditions:

1) The comma is not aligned within the 10-bit transmission character such that Ri(0..6) = “0011111”.

2) The comma straddles the boundary between two 10-bit transmission characters.

3) The comma is properly aligned but occurs in the received character presented during the rising edge of

RCi0 rather than RCi1.

When an improperly aligned comma is encountered, the recovered clock is stretched, never slivered, so that

the comma character and recovered clocks are aligned properly to Ri(0:9). This results in proper character and

word alignment. When the parallel data alignment changes in response to a improperly aligned comma pattern,

G52306-0, Rev. 2.0

3/27/00



VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

Page

VITESSE

SEMICONDUCTOR CORPORATION

Quad Transceiver

for Gigabit Ethernet

Advance Product Information

VSC7186

data which would have been presented on the parallel output port prior to the comma character, and possibly the

comma character itself, may be lost. Possible loss of the comma character is data dependent, according to the

relative change in alignment. Data subsequent to the comma character will always be output correctly and prop-

erly aligned.

On encountering a comma character, SYNi is driven HIGH. The SYNi pulse is presented simultaneously

with the comma character and has a duration equal to the data. The SYNi signal is timed such that it can be cap-

tured by the adjoining protocol logic on the rising edge of RCi1. Functional waveforms for synchronization are

given in Figure 1. The first K28.5 shows the case where the comma is detected, but it is misaligned so a change

in the output data alignment is required. Note that up to three characters prior to the comma character may be

corrupted by the realignment process. The second K28.5 shows the case when a comma is detected and no

phase adjustment is necessary. It illustrates the position of the SYNi pulse in relation to the comma character on

Ri(0:9).

Figure 2: Misaligned and Aligned K28.5 Characters

(RCM LOW)

(RCM HIGH)

SYN

(0:9)

Data

Corrupt

K28.5

Data1

Data2

Data3

K28.5

Misaligned Comma: Stretched

Aligned Comma

Loopback Operation

Loopback operation is controlled by the LOOP line. When this line is HIGH, the outgoing high-speed

serial data on each of the four channels is internally looped back into that channel’s high-speed serial receiver

section. This provides for in-circuit testing capability independent of the transmission medium.

JTAG Access Port

A JTAG access port is provided to assist in board-level testing. Through this port most pins can be accessed

or controlled and all TTL outputs can be tri-stated. A full description of the JTAG functions on this device is

available in “VSC7186 JTAG Access Port Functionality”. Circuits designed exclusively for the HDMP-1686A

will automatically disable the JTAG port. The pinout table in this data sheet shows the proper connections for

either HDMP-1686A emulation or for JTAG functionality (in parentheses).



VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

Page 4

G52306-0, Rev. 2.0

3/27/00

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