19-2245; Rev 0; 10/01
KIT
ATION
EVALU
BLE
AVAILA
Quad ECL/PECL Differential
Buffers/Receivers
General Description
Features
o
Differential Double-Swing ECL/PECL Outputs
o
Input Compatible with LVECL/LVPECL
o
Guaranteed 900mV Differential Output at 3.0GHz
Clock Rate
o
365ps Propagation Delay in Asynchronous Mode
o
10ps Channel-to-Channel Skew in Synchronous
Mode
o
Integrated 100Ω Input Terminations (MAX9404)
o
Compatible +3.3V/+5.0V Nominal Supplies
o
Selectable Synchronous/Asynchronous
Operation
MAX9401/MAX9404
The MAX9401/MAX9404 are extremely fast and low-
skew quad ECL/PECL differential buffers/receivers for
data and clock signals. The four channels can be oper-
ated synchronously with an external clock, or in asyn-
chronous mode, determined by the state of the SEL
input. An enable input provides the ability to force all
the outputs to a differential low state.
The MAX9401 has high-impedance (open) input and
the MAX9404 has an integrated 100Ω differential input
termination, which reduces external component count.
Both devices have double amplitude swing open emit-
ter outputs suitable for driving long cables. The
MAX9401/MAX9404 operate over a V
CC
- V
EE
= +3.0V
to +5.5V supply range, and are specified for operation
from -40°C to +85°C. These devices are offered in
space-saving 32-pin 5mm x 5mm QFN exposed-paddle
(EP) and TQFP packages.
Ordering Information
PART
TEMP.
RANGE
-40°C to
+85°C
-40°C to
+85°C
-40°C to
+85°C
-40°C to
+85°C
PIN-
PACKAGE
32 QFN-EP**
(5mm x 5mm)
32 TQFP
(5mm x 5mm)
32 QFN-EP**
(5mm x 5mm)
32 TQFP
(5mm x 5mm)
INPUT
IMPEDANCE
Open
Open
100Ω
100Ω
Applications
Data and Clock Driver and Buffer
Central Office Backplane Clock Distribution
DSLAM Backplane
Base Station
ATE
MAX9404EHJ
MAX9404EGJ*
MAX9401EGJ*
MAX9401EHJ
Functional Diagram appears at end of data sheet.
*Future
product—contact factory for availability.
**EP
= Exposed paddle
Pin Configurations
OUT0
OUT0
OUT0
V
CC
V
EE
IN0
IN0
IN1
IN1
V
CC
TOP VIEW
OUT0
V
EE
IN0
IN0
32
31
30
29
28
27
26
25
32
31
30
29
28
27
26
IN1
25
24 V
CC
23 OUT1
22 OUT1
21 V
EE
*
V
CC
SEL
SEL
CLK
CLK
EN
EN
V
CC
1
2
3
4
5
6
7
8
*
24
23
22
V
CC
OUT1
OUT1
V
EE
V
EE
OUT2
OUT2
V
CC
V
CC
SEL
SEL
CLK
CLK
EN
EN
V
CC
1
2
3
4
5
6
7
8
9
IN3
10
IN3
11
V
CC
12
OUT3
13
OUT3
14
V
EE
15
IN2
16
IN2
MAX9401/
MAX9404
21
20
19
MAX9401
MAX9404
IN1
20 V
EE
19 OUT2
18 OUT2
17 V
CC
*
18
17
*
10
11
12
13
14
15
IN3
V
EE
IN3
OUT3
OUT3
V
CC
IN2
IN2
16
9
*
QFN-EP*
*EXPOSED PAD AND CORNER PINS ARE CONNECTED TO V
EE
TQFP
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Quad ECL/PECL Differential
Buffers/Receivers
MAX9401/MAX9404
ABSOLUTE MAXIMUM RATINGS
V
CC
to V
EE
.............................................................-0.3V to +6.0V
All Other Pins to V
EE
...................................-0.3V to (V
CC
+ 0.3V)
Differential Input Voltage….................................................±3.0V
Continuous Output Current .................................................70mA
Surge Output Current….. ..................................................100mA
Continuous Power Dissipation (T
A
= +70°C)
32-Pin 5mm x 5mm TQFP (derate 9.5mW/°C
above +70°C)..............................................................761mW
32-Pin 5mm x 5mm QFN-EP (derate 21.3mW/°C
above +70°C)..................................................................1.7W
Junction-to-Ambient Thermal Resistance in Still Air
32-Pin TQFP............................................................+105°C/W
32-Pin QFN-EP…. .....................................................+47°C/W
Junction-to-Ambient Thermal Resistance with
500LFPM Airflow
32-Pin TQFP..............................................................+73°C/W
Junction-to-Case Thermal Resistance
32-Pin TQFP..............................................................+25°C/W
32-Pin QFN-EP… ........................................................+2°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
ESD Protection
Human Body Model (Inputs and Outputs) .................>1.25kV
Soldering Temperature (10s) ...........................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
- V
EE
= +3.0V to +5.5V, outputs terminated with 50Ω ±1% to V
CC
- 3.3V, inputs are driven, unless otherwise noted. Typical val-
ues are at V
CC
- V
EE
= +3.3V, V
IHD
= V
CC
- 0.9V, V
ILD
= V
CC
- 1.7V, T
A
= +25°C, unless otherwise noted.) (Notes 1, 2, 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
V
EE
+
2.0
V
EE
0.2
EN,
EN,
SEL,
SEL,
IN_, IN_,
CLK, or
CLK
= V
IHD
or V
ILD
EN,
EN
, SEL,
SEL,
CLK, or
CLK
= V
IHD
or V
ILD
-10
-10
86
TYP
MAX
UNITS
INPUTS (IN_,
IN_,
CLK,
CLK,
EN,
EN,
SEL,
SEL)
Differential Input High Voltage
Differential Input Low Voltage
Differential Input Voltage
V
IHD
V
ILD
V
ID
Figure 3
Figure 3
Figure 3
MAX9401
Input Current
I
IH
, I
IL
MAX9404
IN to
IN
Differential Input
Resistance
OUTPUTS (OUT_,
OUT_)
Differential Output Voltage
Output Common-Mode Voltage
POWER SUPPLY
Supply Current
I
EE
(Note 4)
84
118
mA
V
OH
- V
OL
V
OCM
Figure 3
Figure 3
1.2
V
CC
-
1.8
1.4
V
CC
-
1.4
V
V
R
IN
MAX9404
V
CC
V
CC
-
0.2
3.0
25
µA
25
114
Ω
V
V
V
2
_______________________________________________________________________________________
Quad ECL/PECL Differential
Buffers/Receivers
AC ELECTRICAL CHARACTERISTICS
(V
CC
- V
EE
= +3.0V to +5.5V, outputs terminated with 50Ω ±1% to V
CC
- 3.3V, outputs are enabled, input transition time = 125ps
(20% to 80%), f
CLK
= 3.0GHz, f
IN
= 1.5GHz, V
IHD
= V
EE
+2.0V to V
CC
, V
ILD
= V
EE
to V
CC
- 0.2V, V
IHD
- V
ILD
= 0.2 to 3.0V, unless oth-
erwise noted. Typical values are at V
CC
- V
EE
= +3.3V, V
IHD
= V
CC
- 0.9V, V
ILD
= V
CC
- 1.7V, T
A
= +25°C, unless otherwise noted.)
(Notes 1, 5)
PARAMETER
IN to OUT Differential
Propagation Delay
CLK to OUT Differential
Propagation Delay
IN to OUT Channel-to-Channel
Skew
CLK to OUT Channel-to-
Channel Skew
Maximum Clock Frequency
Maximum Data Frequency
Added Random Jitter (Note 7)
SYMBOL
t
PLH1
, t
PHL1
t
PLH2
, t
PHL2
t
SKD1
t
SKD2
f
CLK(MAX)
f
IN(MAX)
t
RJ
CONDITIONS
SEL = high, Figure 4
SEL = low, Figure 5
SEL = high (Note 6)
SEL = low (Note 6)
V
OH
- V
OL
≥
900mV, SEL = low
SEL = high, V
OH
- V
OL
≥
900mV
SEL = low, f
IN
= 1.5GHz, f
CLK
= 3.0GHz,
clock
SEL = high, f
IN
= 1.5GHz
Added Deterministic Jitter
(Note 7)
IN to CLK Setup Time
CLK to IN Hold Time
Output Rise Time
Output Fall Time
Propagation Delay Temperature
Coefficient
SEL = low, f
CLK
= 3.0GHz, IN_ = 1.5Gbps,
2
23
-1 PRBS pattern
t
DJ
SEL = high, IN_ = 1.5Gbps, 2
23
-1 PRBS
pattern
Figure 5
Figure 5
Figure 4
Figure 4
80
80
116
115
145
145
1
3.0
1.5
1.4
0.9
20
36
2.5
2.7
30
ps
p-p
55
ps
ps
ps
ps
ps/°C
MIN
300
580
TYP
365
620
15
10
MAX
550
758
55
40
UNITS
ps
ps
ps
ps
GHz
GHz
ps
(RMS)
MAX9401/MAX9404
t
S
t
H
t
R
t
F
∆t
PD
/∆T
Note 1:
Measurements are made with the device in thermal equilibrium.
Note 2:
Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to V
EE
except V
ID
and V
OD
.
Note 3:
DC parameters are production tested at T
A
= +25°C. DC limits are guaranteed by design and characterization over the full
operating range.
Note 4:
Outputs are open. Inputs driven high or low.
Note 5:
Guaranteed by design and characterization. Limits are set to ±6 sigma.
Note 6:
Measured between outputs of the same part at the signal crossing points for a same-edge transition.
Note 7:
Device jitter added to the input signal.
_______________________________________________________________________________________
3
Quad ECL/PECL Differential
Buffers/Receivers
MAX9401/MAX9404
Typical Operating Characteristics
(Outputs terminated with 50Ω to V
CC
- 3.3V, V
CC
- V
EE
= +3.3V, V
IHD
= V
CC
- 0.9V, V
ILD
= V
CC
- 1.7V, output is enabled, SEL = high,
SEL
= low, input transition time = 125ps (20% to 80%), f
CLK
= 3.0GHz, f
IN
= 1.5GHz, T
A
= +25°C, unless otherwise noted.)
DIFFERENTIAL OUTPUT VOLTAGE
(V
OH
- V
OL
) vs. IN_ FREQUENCY
MAX9401/04 toc01
SUPPLY CURRENT vs. TEMPERATURE
100
OUTPUTS ARE OPEN; INPUTS
ARE HIGH OR LOW
94
SUPPLY CURRENT (mA)
1.6
DIFFERENTIAL OUTPUT VOLTAGE (mV)
1.2
88
0.8
82
0.4
76
70
-40
-15
10
35
60
85
TEMPERATURE (°C)
0
0
0.5
1.0
1.5
2.0
2.5
3.0
IN_ FREQUENCY (GHz)
TRANSITION TIME vs. TEMPERATURE
MAX9401/04 toc03
PROPAGATION DELAY
vs. TEMPERATURE
MAX9401/04 toc04
130
700
CLK-TO-OUT DELAY
t
R
118
t
F
PROPAGATION DEALY (ps)
124
TRANSITION TIME (ps)
620
540
112
460
IN-TO-OUT DELAY
106
380
100
-40
-15
10
35
60
85
TEMPERATURE (°C)
300
-40
-15
10
35
60
85
TEMPERATURE (°C)
Pin Description
PIN
1, 8, 11, 17,
24, 30
2
NAME
V
CC
FUNCTION
Positive Supply Voltage. Bypass V
CC
to V
EE
with 0.1µF and 0.01µF ceramic capacitors. Place the
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
Noninverting Differential Select Input. Setting SEL = high and
SEL
= low (differential high) enables
all four channels to operate asynchronously. Setting SEL = low and
SEL
= high (differential low)
enables all four channels to operate in synchronized mode.
Inverting Differential Select Input
Inverting Differential Clock Input. A rising edge on CLK (and falling on
CLK)
transfers data from the
inputs to the outputs when SEL = low.
Noninverting Differential Clock Input
SEL
SEL
CLK
CLK
3
4
5
4
_______________________________________________________________________________________
MAX9401/04 toc02
Quad ECL/PECL Differential
Buffers/Receivers
Pin Description (continued)
PIN
6
7
9
10
12
13
14, 20, 21, 27
15
16
18
19
22
23
25
26
28
29
31
32
—
NAME
EN
EN
IN3
IN3
OUT3
OUT3
V
EE
IN2
IN2
OUT2
OUT2
OUT1
OUT1
IN1
IN1
OUT0
OUT0
IN0
IN0
EP*
FUNCTION
Noninverting Differential Output Enable Input. Setting EN = high and
EN
= low (differential high)
enables the outputs. Setting EN = low and
EN
= high (differential low) sets the outputs to logic low.
Inverting Differential Output Enable Input
Noninverting Differential Input 3
Inverting Differential Input 3
Inverting Differential Output 3
Noninverting Differential Output 3
Negative Supply Voltage
Noninverting Differential Input 2
Inverting Differential Input 2
Inverting Differential Output 2
Noninverting Differential Output 2
Noninverting Differential Output 1
Inverting Differential Output 1
Inverting Differential Input 1
Noninverting Differential Input 1
Noninverting Differential Output 0
Inverting Differential Output 0
Inverting Differential Input 0
Noninverting Differential Input 0
Exposed Paddle. EP is electrically connected to V
EE
. Solder EP to PC board.
MAX9401/MAX9404
*QFN-EP
package only.
Detailed Description
The MAX9401/MAX9404 are extremely fast, low-skew
quad ECL/PECL buffers/receivers designed for high-
speed data and clock driver applications. These
devices feature ultra-low propagation delay of 365ps
and channel-to-channel skew of 15ps in asynchronous
mode with 84mA supply current, making them ideal for
driving long cables and double termination applications
(Functional
Diagram).
The four channels can be operated synchronously with
an external clock, or in asynchronous mode, deter-
mined by the state of the SEL input. An enable input
provides the ability to force all the outputs to a differen-
tial low state.
Data Input Termination
Figure 1 shows the input and output configuration of
the MAX9401/MAX9404. The MAX9401 has high-
impedance inputs and requires external termination.
The MAX9404 has integrated 100Ω differential input
termination resistors across each of the four inputs (IN_
to
IN_),
reducing external component count.
Outputs
The MAX9401/MAX9404 have double-swing open-emit-
ter outputs as shown in Figure 1. The double-amplitude
swing outputs can drive double-terminated links or long
5
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