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TMC2081
Digital Video Mixer
Features
• Mixes 24//16-bit GBR/YC
B
C
R
444//YC
B
C
R
422 and 8-bit
color-index sources
• 24//16-bit GBR/YC
B
C
R
444//YC
B
C
R
422 output
• 255-step proportional mixing via
a
7-0
inputs
• 256-step mixing with
a
8-0
for
a
=100h unity gain
• 256 x 8-bit look-up table on
a
channel
• Lap-dissolve and fade effects
•
a
and crosspoint controls for soft and color-border wipe
generation
• Mask register and three 256 x 8 bypassable CLUTs with
overlay on A-channel
• Analog preview output with sync on Green/Y
• D/A power-down modes
• Single +5 volt power supply operation
• Pin compatible with TMC22080 Digital Mixer
Description
The TMC2081 is a Digital Video Mixer that performs
M
= (
a
)
V
1
+ ( 1-
a
)
V
2
(for 0
£ a £
1)
cross-fading at speeds faster than 40 Mpps proportionally
controlled by a 9-bit
a
-channel input. Variable rate dissolves
and fades may be implementedwith unity gain at the
a
end-
points. With the
a
-Look-Up Table (
a
LUT), mixing may be
controlled by a single bit of the
a
-channel input. Setup is via
a microprocessor interface.
Supported video formats are 24-bit GBR, YC
B
C
R
444, and
16-bit YC
B
C
R
422 component video. Dissimilar pixel for-
mats may be mixed using on-chip interpolation and decima-
tion filters and GBR/YC
B
C
R
and YC
B
C
R
/GBR color-space
conversion matrices.
An additional format accepted by the A-channel is 8-bit
color-indexed pixel data which addresses three bypassable
256 x 8 color look-up tables (CLUTs). A 15 color overlay
palette and a 24-bit fill register are also included.
Digital and Analog outputs may be programmed to view
either mixer inputs, V
1
or V
2
or mixer output, M.
Packaged in a 128-lead plastic metric quad flat-pack
(MQFP), the TMC2081 is fabricated with a sub-micron
CMOS process. Performance is guaranteed over the com-
mercial, 0
°
C to 70
°
C temperature range.
Applications
•
•
•
•
Mixing computer graphics and live video
Lap-dissolve between video sources
Fade to black or to user-selectable fill color
Window/wipe processing
Logic Symbol
DATA
INPUTS
PDA23-0
PDB23-0
a
8-0
AV
PASSEN
SIG0
CLK
OL3-0
SMX2-0
SYNC
BLANK
D7-0
D2-0
CS
R/W
COMP
VREF
RREF
D/A
SETUP
M23-0
PASS14
SIG14
AVOUT
VIDEO
OUTPUT
TIMING
INPUTS
MICRO-
ANALOG OVERLAY
PROCESSOR TIMING & CONTROL
INTERFFACE
TMC2081
DIGITAL
VIDEO
MIXER
ANALOG
OUTPUTS
G/Y
B/CB
R/CR
65-2081-01
Rev. 1.3.0
Block Diagram
VREF
RREF
COMP
2
TMC2081
PASS14
SIG14
AVOUT
Delay
Unity Gain
Switch
RGB
YCbCr
Matrix
Source
Select
444
422
Decimator/
Filter
A
F
Crosspoint
Switch
V2
V1
Triple Dual
Input 9-bit
a-Mixer
A
M
B
444
422
Formatter
M23-0
Fill
Register
YCbCr
RGB
Matrix
B
M
D/A
A
B
YCbCr
RGB
Matrix
DAC
Formatter
2's
OSB
D/A
D/A
B/CB
R/CR
REF
G/Y
PASSEN
SIG0
Register
Delay
AV
SMX2-0
Delay
a
8-0
a
Register
a
LUT
PDA23-0
A Register/
Formatter
256x8x3
CLUT
Mask
Register
15x8x3
Overlay
Table
OL3-0
PDB23-0
B Register/
Formatter
422
444
Interpolator/
Filter
SYNC
BLANK
Delay
(2/15 clock)
CLK
D7-0
A2-0
CS
R/W
Microprocessor
Interface
PRODUCT SPECIFICATION
65-2081-02
PRODUCT SPECIFICATION
TMC2081
Functional Description
The TMC2081 is a monolithic digital video processor that
proportionally mixes digital video in GBR, YC
B
C
R
, or color-
index formats. Some of the variety of input and output data
format combinations are shown in Table 1.
The A-channel data path has transformation circuits that can
look up 24-bit GBR values from 8-bit color-index inputs,
convert GBR-to-YC
B
C
R
format, and decimate YC
B
C
R
444 to
YC
B
C
R
422. The B-channel path includes circuits that
convert YC
B
C
R
to GBR and interpolate YC
B
C
R
422 to
YC
B
C
R
444. Prior to mixing, incoming pixel data streams
must be converted to matching formats by setting the A and
B channel control registers.
Data enters the TMC2081 through the PDA
23-0
, PDB
23-0
,
a
8-0
, and OL
3-0
ports. Data and video controls (PASSEN and
AV) are simultaneously registered on the rising edge of
PXCLK. Pipeline latency is 14 clock cycles to the mixed
digital video output.
Although PDA
23-0
, PDB
23-0
, and M
23-0
data formats may be
different, V
1
and V
2
data formats at the
a
-Mixer input must
be matched: unsigned magnitude for GBR and Y
components; 2’s complement for C
B
and C
R
components.
Data formats converted within the TMC2081 are determined
by the control bits programmed into the internal registers.
Output format may be GBR, YC
B
C
R
444 or YC
B
C
R
422.
Either crosspoint switch input, A and B or the Mixer output
may be selected at the M
23-0
port. Table 2, Table 3 and Table
4 show examples of the M
23-0
output for 9-bit
a
-mixing. In
Table 3, C
B
C
R
is accepted at the C
B
input. Table 4 exempli-
fies format
conversion.
Mixer output and inputs may be previewed by three video
D/A converters. Analog outputs may be either GBR or
YC
B
C
R
.
For initialization and control, internal registers and tables
may be accessed through a microprocessor interface.
Power may be conserved by disabling the D/A converters or
sections of the TMC2081 via internal Control Registers.
In the latter mode, the microprocessor interface remains
active and Control Register settings are retained but CLUT
locations are not accessible.
Table 1. Input and Output Data Format Examples
A Input
Format
B Input
Format
A
A
A
B
B
M
CLUT GBR-YC
B
C
R
Decimate Interpolate YC
B
C
R
-GBR Format
Bypass
Bypass
Bypass
Bypass
Bypass
Bypass
Enable
Bypass
Enable
Bypass
Bypass
Bypass
Enable
Bypass
Bypass
Bypass
Bypass
Bypass
Enable
Bypass
Bypass
Enable
Bypass
Bypass
Bypass
Bypass
Bypass
Enable
Bypass
Bypass
Bypass
Bypass
Bypass
Bypass
Bypass
Enable
Bypass
Enable
Bypass
Bypass
Low
Low
High
High
Low
Low
Low
Low
High
Low
M Output
Format
YC
B
C
R
444
YC
B
C
R
444
YC
B
C
R
422
YC
B
C
R
422
YC
B
C
R
444
GBR
YC
B
C
R
444
GBR
YC
B
C
R
422
GBR
YC
B
C
R
444 YC
B
C
R
444 Bypass
YC
B
C
R
444 YC
B
C
R
422 Bypass
YC
B
C
R
444 YC
B
C
R
422 Bypass
YC
B
C
R
422 YC
B
C
R
422 Bypass
YC
B
C
R
422 YC
B
C
R
422 Bypass
GBR, CI
GBR, CI
GBR, CI
GBR, CI
GBR, CI
YC
B
C
R
444 Enable
YC
B
C
R
444 Enable
YC
B
C
R
422 Enable
YC
B
C
R
422 Enable
GBR
Enable
Table 2. GBR Mixing Example (9-bit
a
)
a
(hex)
000
040
080
100
PDA (hex)
G
BB
BB
BB
BB
B
CC
CC
CC
CC
R
AA
AA
AA
AA
G
EE
EE
EE
EE
PDB (hex)
B
FF
FF
FF
FF
R
DD
DD
DD
DD
G
EE
E1
D5
BB
M (hex)
B
FF
F2
E6
CC
R
DD
D0
C4
AA
3
TMC2081
PRODUCT SPECIFICATION
Table 3. YC
B
C
R
422 Mixing Example (C
B
and C
R
in 2’s Complement)
a
(hex)
40
80
40
40
A0
B0
A0
B0
Y
10
10
10
10
30
30
30
30
PDA (hex)
C
B
F4
F4
F4
FE
60
80
C0
E0
C
R
XX
XX
XX
XX
XX
XX
XX
XX
Y
20
20
20
20
40
40
40
40
PDB (hex)
C
B
4
4
4
2
70
90
D0
F0
C
R
XX
XX
XX
XX
XX
XX
XX
XX
Y
1C
18
1C
1C
36
35
36
35
M (hex)
C
B
00
00
00
01
66
86
C6
E5
C
R
00
00
00
00
00
00
00
00
Table 4. YC
B
C
R
422-to-YC
B
C
R
444 Mixing Example
a
(hex)
40
40
40
40
A0
B0
A0
B0
Y
10
10
10
10
30
30
30
30
PDA (hex)
C
B
F4
F4
F4
FE
60
80
C0
E0
C
R
XX
XX
XX
XX
XX
XX
XX
XX
Y
20
20
20
20
40
40
40
40
PDB (hex)
C
B
4
4
4
2
70
90
D0
F0
C
R
XX
XX
XX
XX
XX
XX
XX
XX
Y
1C
1C
1C
1C
36
35
36
35
M (hex)
C
B
00
00
00
00
66
66
C6
C6
C
R
00
00
01
01
86
86
E5
E5
Input Formats
Data is accepted by PDA and PDB channels in one pair of
the following formats:
1.
2.
3.
4.
YC
B
C
R
444
YC
B
C
R
422
GBR
8-bit color-index mapped to a palette of 256x256x256
colors. (A-channel only)
Details of bits assignments are shown in Figure 1. Pixel Data
Formats with the expected data ranges are shown in Table 5.
Table 5. YC
B
C
R
and GBR Data Types and
Ranges
Signal
GBR
Y
C
B
C
R
Min.
0
16
-112
Max.
255
235
+112
Format
Unsigned Binary
Unsigned Binary
2’s Complement
Offset Binary
23
YC
B
C
R
444
YC
B
C
R
422
GBR
Color Index
(A-channel only)
Y7
Y7
G7
16 15
Y0 CB7
C
Y0 CB7
R7
G0 B7
8
7
0
CR0
CB0 CR7
CB0
CR0
B0
R7
P7
R0
P0
65-2081-03
Figure 1. Pixel Data Formats
4
PRODUCT SPECIFICATION
TMC2081
A-Channel Operation
A-channel pixel data, PDA, is registered on the rising edge
of CLK. C
B
C
R
data is either passed or format converted
(from offset binary to 2’s complement) by MSB inversion.
16-bit YC
B
C
R
422 data is converted to 24-bit YC
B
C
R
data
by pixel replication of C
B
C
R
data. Each of the three A chan-
nel bytes is logically-ANDed with the contents of the Mask
Register.
The CLUT in the A-channel pixel data path comprises three
256-word x 8-bit sections. When the CLUT is enabled, pixel
data addresses the CLUT, which outputs the address contents
for subsequent processing. The CLUT may also be bypassed,
passing incoming pixel data directly to subsequent circuits.
For 24-bit GBR operation, each of the 256-word by 8-bit
CLUTs is independently addressed by green, blue, and red
bytes from PDA
23-0
. For Color-index operation, each of the
256 x 8 CLUTs is addressed by the same pixel data from
PDA
7-0
.
CLUT locations may hold GBR or YC
B
C
R
color values. V
1
and V
2
mixer input formats must match CLUT formats.
The PDA overlay palette is addressed by four Overlay
inputs, OL
3-0
and is enabled via the Control Register. Each
valid Overlay address produces one of 15 24-bit colors
selected from stored 8-bit red, green, and blue values. If all
four overlay inputs are LOW, CLUT data is selected. If any
overlay input is HIGH, OL
3-0
is decoded into the corre-
sponding color which is selected at the RGB/YC
B
C
R
matrix.
OL
3-0
may be changed on a pixel-by-pixel basis.
Table 7. B-Channel YC
B
C
R
-GBR Mapping for
Fully-Saturated Colors
Input Values
Color
White
Yellow
Cyan
Green
Magenta
Red
Blue
Black
Y
235
210
169
144
106
81
41
16
C
B
0
-112
38
-74
74
-38
112
0
C
R
0
18
-112
-94
94
112
-18
0
Output Values
R
255
255
0
0
255
255
0
0
G
255
255
255
255
0
0
0
0
B
255
0
255
0
255
0
255
0
B-Channel Operation
YC
B
C
R
444, YC
B
C
R
422, or GBR are accepted by the
B-channel. PDB
23-0
pixel data is registered on the rising
edge of CLK. 16-bit YC
B
C
R
422 data is converted to 24-bit
YC
B
C
R
444 data by pixel replication of C
B
C
R
data in the
Register/Formatter.
24-bit data is passed to an interpolation filter followed by
a color-space converter to ensure that the B-channel data
format matches that of the A-channel prior to mixing.
Table 1 illustrates the setup of color-space converters,
decimation, and interpolation filters. Pipeline latencies
of the A and B-channels are matched.
Interpolation and Decimation Filters
Digital interpolation and decimation filters in the A- and
B-channels suppress unwanted artifacts in the chrominance
components. Maximum passband attenuation is
0.06 dB. Minimum stopband rejection is 41 dB.
When the input format is YC
B
C
R
422, the incoming pixel
following AV transitioning HIGH is assumed to be the C
B
pixel. (See Figure 11.)
Table 6. A-Channel GBR-to-YC
B
C
R
Mapping
for Fully-Saturated Colors
Input Values
Color
White
Yellow
Cyan
Green
Magenta
Red
Blue
Black
R
255
255
0
0
255
255
0
0
G
255
255
255
255
0
0
0
0
B
255
0
255
0
255
0
255
0
Output Values
Y
235
210
169
144
106
81
41
16
CB
0
-112
38
-74
74
-38
112
0
CR
0
18
-112
-94
94
112
-18
0
a-Channel
Operation
Nine bits of
a
data are registered on a pixel-by-pixel basis
from
a
8-0
. Either 9-bit or 8-bit
a
values can be selected by
setting Control Register Bit
aGAIN.
Table 8 shows the dif-
ferences between the 8-bit and 9-bit gain settings for a 0FF
input.
Bits
a
7-0
address a 256 x 8-bit lookup table (aLUT).
The
aLUT
may be used to redefine the function of incoming
a
data for special effects or low resolution dissolves and
fades.
Bit
a
8
controls a unity gain switch. If
a
8
= 1, then
a
is set
to unity gain.
a
8
functions independently of the
a
gain bit
register 0. For 8-bit
a
mixing, set
a
8
= 0.
By setting control register bit
aLUTEN
= 0, the
aLUT
may
be completely bypassed, allowing
a
8-0
to directly control the
mixing of A, B and F.
aLUT
locations may be accessed via
the D
7-0
microprocessor port.
5
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