HANBit
HSD32M64F8V/VA
Synchronous DRAM Module, 256Mbyte ( 32M x 64-Bit ) SMM based
on 32Mx8, 4Banks, 8K Ref., 3.3V
Part No.
HSD32M64F8V/VA
GENERAL DESCRIPTION
The HSD32M64F8V/VA is a 32M x 64 bit Synchronous Dynamic RAM high density memory module. The module
consists of eight CMOS 8M x 8 bit with 4banks Synchronous DRAMs in TSOP-II packages is mounted on a 120-pin,
double-sided, FR-4-printed circuit board., Two 0.1uF decoupling capacitors are mounted on the printed circuit board in
parallel for each SDRAM. The HSD32M64F8V/VA is a SMM (Stackable Memory Module) designed and is intended for
mounting into two 60-pin connector sockets. Synchronous design allows precise cycle control with the use of system clock.
I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the
same device to be useful for a variety of high bandwidth, high performance memory system applications All module
components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.
FEATURES
•
Part Identification
PIN
HSD32M64F8V :
Stacking Height ( T = 11.3mm )
HSD32M64F8VA :
Stacking Height ( T = 7.3mm )
•
Burst mode operation
•
Auto & self refresh capability (8192 Cycles/64ms)
•
LVTTL compatible inputs and outputs
•
Single 3.3V
±0.3V
power supply
•
MRS cycle with address key programs
- Latency (Access from column address)
- Burst length (1, 2, 4, 8 & Full page)
- Data scramble (Sequential & Interleave)
•
All inputs are sampled at the positive going edge
of the system clock
•
120pin-SMM type FR4-PCB design
•
The used device is 32Mx8bit SRAM
•
Pin assignment is compatible with
- HSD8M64F8V
- HSD16M64F8V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Symbol
Vcc
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
Vcc
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
Vcc
DQM4
DQM5
NC
CKE0
CKE1
Vcc
NC
NC
/CE2
NC
Vcc
PIN ASSIGNMENT
60-PIN P1 Connector
PIN
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Symbol
Vss
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Vss
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Vss
DQM0
DQM1
/WE
CLK0
CLK1
Vss
/CAS
/RAS
/CE0
NC
Vss
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
60-PIN P2 Connector
Symbol
Vss
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
Vss
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
Vss
DQM2
DQM3
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
Vss
PIN
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Symbol
Vcc
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
Vcc
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
Vcc
DQM6
DQM7
A12
A11
A9
A8
A7
A6
A5
A4
Vcc
Stackable Memory Module TOP VIEW
URL:www.hbe.co.kr
REV.1.0 (August.2002)
1
HANBit Electronics Co.,Ltd.
HANBit
FUNCTIONAL BLOCK DIAGRAM
DQ0-63
HSD32M64F8V/VA
CKE0
/CAS
CKE
CAS
RAS
CE
CKE
CAS
RAS
WE
U1
A0-A12
CLK
DQ0-7
DQM0
BA0-1
CLK
DQ32-39
CLK0
DQM0
/RAS
/CE0
CLK1
DQM4
U2
WE
A0-A12
DQM4
BA0-1
CLK
DQ16-23
/CE2
CE
CKE
CAS
RAS
CE
U3
WE
A0-A12
DQM2
BA0-1
DQM2
CKE
CAS
RAS
CE
WE
CLK
DQ48-55
U4
A0-A12
DQM6
BA0-1
DQM6
CKE
CAS
RAS
CE
CKE
CAS
RAS
CE
CKE
CAS
RAS
CE
WE
WE
WE
CLK
DQ8-15
U5
A0-A12
DQM1
BA0-1
CLK
DQ40-47
DQM1
U6
A0-A12
DQM5
BA0-1
CLK
DQ24-31
DQM5
U7
A0-A12
DQM3
BA0-1
DQM3
CKE
CAS
RAS
CE
WE
CLK
DQ56-63
U8
A0-A12
DQM7
BA0-1
DQM7
/WE
A0 - A12
BA0-1
Vcc
Vss
Two 0.1uF Capacitors
per each SDRAM
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REV.1.0 (August.2002)
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HANBit Electronics Co.,Ltd.
HANBit
PIN FUNCTION DESCRIPTION
Pin
CLK
/CE
Name
System clock
Chip enable
Input Function
HSD32M64F8V/VA
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tSS prior to valid command.
A0 ~ A12
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9
BA0 ~ BA1
Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
/RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
/CAS
Column
strobe
address
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
/WE
Write enable
DQM0 ~ 7
Data
mask
input/output
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
DQ0 ~ 63
Vcc/Vss
Data input/output
Power
supply/ground
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Power Dissipation
Storage Temperature
SYMBOL
V
IN ,OUT
Vcc
P
D
T
STG
RATING
-1V to 4.6V
-1V to 4.6V
8W
-55oC to 150oC
Short Circuit Output Current
I
OS
400mA
Notes :
Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
URL:www.hbe.co.kr
REV.1.0 (August.2002)
3
HANBit Electronics Co.,Ltd.
HANBit
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70° C) )
PARAMETER
Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
SYMBOL
Vcc
V
IH
V
IL
V
OH
V
OL
MIN
3.0
2.0
-0.3
2.4
-
TYP.
3.3
3.0
0
-
-
MAX
3.6
Vcc+0.3
0.8
-
0.4
HSD32M64F8V/VA
UNIT
V
V
V
V
V
NOTE
1
2
I
OH
= -2mA
I
OL
= 2mA
3
Input leakage current
I
LI
-10
-
10
uA
Notes :
1. V
IH
(max) = 5.6V AC. The overshoot voltage duration is
≤
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
DDQ
.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VCC = 3.3V, TA = 23° C, f = 1MHz, VREF =1.4V
±
200 mV)
DESCRIPTION
Clock
Address
/RAS, /CAS, /WE, /CS, CKE, DQM
DQ (DQ0 ~ DQ15)
SYMBOL
C
CLK
C
ADD
C
IN
C
OUT
MIN
20
20
20
32
MAX
32
40
40
52
UNITS
pF
pF
pF
pF
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REV.1.0 (August.2002)
4
HANBit Electronics Co.,Ltd.
HANBit
DC CHARACTERISTICS
HSD32M64F8V/VA
(Recommended operating condition unless otherwise noted, TA = 0 to 70° C)
TEST
PARAMETER
SYMBOL
CONDITION
Burst length = 1
Operating current
(One bank active)
I
CC1
t
RC
≥
t
RC
(min)
I
O
= 0mA
I
CC2
P
CKE
≤
V
IL
(max)
t
CC
=10ns
CKE & CLK
≤
V
IL
(max)
t
CC
=∞
CKE
≥
V
IH
(min)
I
CC2
N
Precharge standby current in
one time during 20ns
non power-down mode
I
CC2
NS
CKE
≥
V
IH
(min)
CLK
≤
V
IL
(max),
t
CC
=∞
112
mA
CS*
≥
V
IH
(min),
t
CC
=10ns
128
16
mA
16
mA
960
960
880
880
mA
1
-13
-12
-10
-10L
VERSION
UNIT
NOTE
Precharge standby current in
power-down mode
I
CC2
PS
Input signals are changed
Input signals are stable
Active
standby
current
in
I
CC3
P
I
CC3
PS
CKE
≤
V
IL
(max), t
CC
=10ns
CKE&CLK
≤
V
IL
(max)
t
CC
=∞
CKE≥V
IH
(min),
I
CC3
N
CS*≥V
IH
(min),
t
CC
=10ns
240
mA
48
mA
48
power-down mode
Active standby current in
non power-down mode
(One bank active)
Input signals are changed
one time during 20ns
CKE≥VIH(min)
I
CC3
NS
CLK
≤VIL(max),
t
CC
=∞
200
Input signals are stable
I
O
= 0 mA
Operating current
(Burst mode)
I
CC4
Page burst
1120
4Banks Activated
t
CCD
= 2CLKs
Refresh current
Self refresh current
I
CC5
I
CC6
t
RC
≥
t
RC
(min)
CKE
≤
0.2V
1680
1680
40
16
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noticed, input swing level is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ
).
URL:www.hbe.co.kr
REV.1.0 (August.2002)
HANBit Electronics Co.,Ltd.
1120
920
920
mA
1
1600
1600
mA
mA
mA
2
5
FPGA/CPLD
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