HANBit
HMN4M8DV(N)
Non-Volatile SRAM MODULE 32Mbit (4,096K x 8-Bit), 40Pin-DIP, 3.3V
Part No. HMN4M8DV(N)
GENERAL DESCRIPTION
The HMN4M8DV Nonvolatile SRAM is a 33,554,432-bit static RAM organized as 4,194,304 bytes by 8 bits.
The HMN4M8DV has a self-contained lithium energy source provide reliable non -volatility coupled with the unlimited write
cycles of standard SRAM and integral control circuitry which constantly monitors the single 3.3V supply for an out-of-
tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on to sustain the
memory until after V
CC
returns valid and write protection is unconditionally enabled to prevent garbled data. In addition the
SRAM is unconditionally write-protected to prevent an inadvertent write operation. At this time the integral energy source
is switched on to sustain t he memory until after V
CC
returns valid.
The HMN4M8DV uses extremely low standby current CMOS SRAM’s, coupled with small lithium coin cells to provide non -
volatility without long write-cycle times and the write-cycle limitations associated with EEPROM.
FEATURES
w
Access time : 55, 70ns
w
High-density design : 32Mbit
Design
w
Battery internally isolated until
power is applied
w
Industry-standard 40-pin 4,096K
x 8 pinout
w
Unlimited write cycles
w
Data retention in the absence of
V
CC
w
5-years minimum data retention
in absence of power
w
Automatic write-protection during
power-up/power-down cycles
w
Data is automatically protected
during power loss
PIN ASSIGNMENT
A
21
A
20
A
18
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
V
CC
A
19
NC
A
15
A
17
/WE
A
13
A
8
A
9
A
11
/OE
A
10
/CE
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
NC
A
21
A
20
A
18
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
V
CC
A
19
NC
A
15
A
17
/WE
A
13
A
8
A
9
A
11
/OE
A
10
/CE
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
NC
36-pin Encapsulated Package
w
Package Option
- HMN4M8DV
- HMN4M8DVN
- 36 Pin DIP Package
- 40 Pin DIP Package
40-pin Encapsulated Package
URL : www.hbe.co.kr
Rev. 1.0 (May, 2002)
1
HANBit Electronics Co.,Ltd
HANBit
FUNCTIONAL DESCRIPTION
HMN4M8DV(N)
The HMN4M8DV executes a read cycle whenever /WE is inactive(high) and /CE is active(low). The address specified by
the address inputs(A
0
-A19) defines which of the 4,194,304 bytes of data is accessed. Valid data will be a vailable to the
eight data output drivers within t
ACC
(access time) after the last address input signal is stable.
When power is valid, the HMN4M8DV operates as a standard CMOS SRAM. During power -down and power-up cycles,
the HMN4M8DV acts as a nonvolatile memory, automatically protecting and preserving the memory contents.
The HMN4M8DV is in the write mode whenever the /WE and /CE signals are in the active (low) state after address inputs
are stable. The later occurring falling edge of /CE or /WE will d etermine the start of the write cycle. The write cycle is
terminated by the earlier rising edge of /CE or /WE. All address inputs must be kept valid throughout the write cycle. WE
must return to the high state for a minimum recovery time (t
WR
) before another cycle can be initiated. The /OE control
signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus been enabled
(/CE and /OE active) then /WE will disable the outputs in t
ODW
from its falling edge.
The HMN4M8DV provides full functional capability for V cc greater than 4.5 V and write protects by 4.37 V nominal.
Power-down/power-up control circuitry constantly monitors the V cc supply for a power-fail-detect threshold V
PFD
. When
V
CC
falls below the V
PFD
threshold, the SRAM automatically write -protects the data. All inputs to the RAM become
“don’t
care” and all outputs are high impedance. As V cc falls below approximately 3 V, the power switching circuit connects the
lithium energy soure to RAM to retain d ata. During power-up, when Vcc rises above approximately 3.0 volts, the power
switching circuit connects external V cc to the RAM and disconnects the lithium energy source. Normal RAM operation
can resume after Vcc exceeds 4.5 volts.
BLOCK DIAGRAM
PIN DESCRIPTION
A
0
-A
19
/OE
/WE
Power
/CE
A
20
-A
21
Power
–
Fail
Control
Lithium
Cell
(1M x 8) x 4
SRAM
Block CE2
/CE1
/CE
CON
V
CC
DQ
0
-DQ
7
A
0
-A
21
: Address Input
/CE : Chip Enable
V
SS
: Ground
DQ
0
-DQ
7
: Data In / Data Out
/WE : Write Enable
/OE : Output Enable
V
CC
: Power (+5V)
NC : No Connection
URL : www.hbe.co.kr
Rev. 1.0 (May, 2002)
2
HANBit Electronics Co.,Ltd
HANBit
TRUTH TABLE
MODE
Not selected
Output disable
Read
Write
/OE
X
H
L
X
/CE
H
L
L
L
CE2
X
H
H
H
/WE
X
H
H
L
HMN4M8DV(N)
I/O OPERATION
High Z
High Z
D
OUT
D
IN
POWER
Standby
Active
Active
Active
ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC voltage applied on V
CC
relative to V
SS
DC Voltage applied on any pin excluding V
CC
relative
to V
SS
Operating temperature
Storage temperature
Temperature under bias
Soldering temperature
NOTE:
SYMBOL
V
CC
V
T
RATING
-0.5V to V
CC
+0.2V
-0.2V to 4.6V
0 to 70°C
-40 to 85°C
-65°C to 150°C
-40°C to 85°C
260°C
For 10 second
Commercial
Industrial
CONDITIONS
T
OPR
T
STG
T
BIAS
T
SOLDER
Permanent device damage may occur if Absolute Maximum Ratings are exceeded.
Functional operation should be restricted to the Recommended DC Operating Conditions detailed in this data sheet.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS ( T
A
= T
OPR
)
PARAMETER
Supply Voltage
Ground
Input high voltage
Input low voltage
NOTE:
SYMBOL
V
CC
V
SS
V
IH
V
IL
MIN
3.0V
0
2.2
-0.2
2)
TYPICAL
3.3V
0
-
-
MAX
3.6V
0
V
CC
+0.3V
0.6V
1)
1. Overshoot: VCC+2.0V in case of pulse width
≤20ns.
3. Overshoot and undershoot are sampled, not 100% tested.
2. Undershoot: -2.0V in case of pulse width
≤20ns.
URL : www.hbe.co.kr
Rev. 1.0 (May, 2002)
3
HANBit Electronics Co.,Ltd
HANBit
CAPACITANCE
(T
A
=25℃ , f=1MHz)
DESCRIPTION
Input Capacitance
Input/Output Capacitance
CONDITIONS
Input voltage = 0V
Output voltage = 0V
SYMBOL
C
IN
C
I/O
MAX
8
10
HMN4M8DV(N)
MIN
-
-
UNIT
pF
pF
NOTE:
1. Capacitance is sampled, not 100% tested.
DC AND OPERATION CHARACTERISTICS
(T
A
= T
OPR
, V
CCmin
£
V
CC
≤
V
CCmax
)
PARAMETER
Input Leakage Current
Output Leakage Current
Output high voltage
Output low voltage
Standby supply current
CONDITIONS
V
IN
=V
SS
to V
CC
/CE=V
IH
or /OE=V
IH
or /WE=V
IL
I
OH
=-1.0 mA
I
OL
= 2.1 mA
/CE≥ V
CC
-0.2V
Cycle time=Min, 100% duty,
I
I/O
=0㎃ ,
/CE<V
cc
-0.2V,
Average operating current
V
IN
<0.2V or V
IN
>V
CC
-0.2V
Cycle time=1us, 100% duty,
I
I/O
=0㎃ ,
/CE=V
IL
, V
IN
=V
IL
or V
IH
Power-fail-detect voltage
Supply switch-over voltage
V
PFD
V
SO
2.5
-
2.6
3
2.7
-
V
V
I
CC2
-
-
50
㎃
I
CC1
-
-
12
㎃
SYMBOL
I
LI
I
LO
V
OH
V
OL
I
SB1
MIN
-4
-4
2.4
-
-
TYP.
-
-
-
-
-
MAX
+4
+4
-
0.4
80
UNI
T
mA
mA
V
V
mA
CHARACTERISTICS
(Test Conditions)
PARAMETER
Input pulse levels
Input rise and fall times
Input and output timing
reference levels
Output load
(including scope and jig)
See Figure 1 and 2
VALUE
0 to 3V
< 5 ns
1.5V
( unless otherwise specified)
Figure 1.
Output Load A
1KΩ
D
OUT
1.9KΩ
+5V
D
OUT
100㎊
+5V
1.9KΩ
5㎊
1KΩ
Figure 2.
Output Load B
URL : www.hbe.co.kr
Rev. 1.0 (May, 2002)
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HANBit Electronics Co.,Ltd
HANBit
READ CYCLE
(T
A
= T
OPR
, V
CCmin
£
V
CC
≤
V
CCmax
)
PARAMETER
Read Cycle Time
Address Access Time
Chip enable access time
Output enable to Output valid
Chip enable to output in low Z
Output enable to output in low Z
Chip disable to output in high Z
Output disable to output high Z
Output hold from address change
SYMBOL
t
RC
t
ACC
t
ACE
t
OE
t
CLZ
t
OLZ
t
CHZ
t
OHZ
t
OH
Output load A
Output load A
Output load A
Output load B
Output load B
Output load B
Output load B
Output load A
CONDITIONS
-70
MIN
70
-
-
-
5
5
0
0
10
MAX
-
70
70
35
-
-
25
25
-
MIN
85
-
-
-
5
0
0
0
10
-85
MAX
-
85
85
45
-
-
35
25
-
HMN4M8DV(N)
-120
MIN
120
-
-
-
5
0
0
0
10
MAX
-
120
120
60
-
-
45
35
-
-150
MIN
150
-
-
-
10
5
0
0
10
MAX
-
150
150
70
-
-
60
50
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRITE CYCLE
(T
A
= T
OPR
, V
ccmin
£
V
cc
≤
V
ccmax
)
PARAMETER
Write Cycle Time
Chip enable to end of write
Address setup time
Address valid to end of write
Write pulse width
Write recovery time (write cycle 1)
Write recovery time (write cycle 2)
Data valid to end of write
Data hold time (write cycle 1)
Data hold time (write cycle 2)
Write enabled to output in high Z
Output active from end of write
SYMBOL
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR1
t
WR2
t
DW
t
DH1
t
DH2
t
WZ
t
OW
Note 4
Note 4
Note 5
Note 5
Note 1
Note 2
Note 1
Note 1
Note 3
Note 3
CONDITIONS
-70
MIN
70
65
0
65
55
5
15
30
0
10
0
5
MAX
-
-
-
-
-
-
-
-
-
-
25
-
MIN
85
75
0
75
65
5
15
35
0
10
0
0
-85
MAX
-
-
-
-
-
-
-
-
-
-
30
-
-120
MIN
120
100
0
100
85
5
15
45
0
10
0
0
MAX
-
-
-
-
-
-
-
-
-
-
40
-
-150
Min
150
100
0
90
90
5
15
50
0
0
0
5
Max
-
-
-
-
-
-
-
-
-
-
50
-
UNI
T
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE:
1. A write ends at the earlier transition of /CE going high and /WE going high.
2. A write occurs during the overlap of allow /CE and a low /WE. A write begins at t he later transition of /CE
going low and /WE going low.
3. Either t
WR1
or t
WR2
must be met.
4. Either t
DH1
or t
DH2
must be met.
5. If /CE goes low simultaneously with /WE going low or after /WE going low, the outpu ts remain in high-
impedance state.
URL : www.hbe.co.kr
Rev. 1.0 (May, 2002)
5
HANBit Electronics Co.,Ltd
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