HANBit
HMD2564Z1
1Mbit(256x4bit) Fast Page Mode, 1K Refresh, 20Pin ZIP, 5V Design
Part No. HMD2564Z1
DESCRIPTION
The HMD2564Z1 is an 256K x 4 bits Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of
memory cells
within the same row. Power supply voltage (+5V ), access time (-5, -6), power consumption(Normal or Low power), and package
type (ZIP)
are optional features of this Module. The HMD2564Z1 have CAS-before-RAS refresh, RAS-only refresh and Hidden
refresh capabilities.
The HMD2564Z1 is optimized for application to the systems, which are required high density and large capacity such as main
memory for main frames and mini computers, personal computer and high performance microprocessor systems.
The HMD2564Z1 provides common data and outputs.
Features
w
Fast Page Mode operation
w
CAS-before-RAS refresh capability
w
RAS-only and Hidden refresh capability
w
Fast parallel test mode capability
w
TTL(5V) compatible inputs and outputs
w
Early write or output enable controlled write
w
Available in 20pin ZIP packages
w
Single +5V± 10% power supply
w
1,024 Refresh Cycles/16ms
w
Performance Range
Speed
HMD2564Z1-5
HMD2564Z1-6
t
RAC
50
60
t
CAC
15
15
t
RC
90
110
t
PC
35
40
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
PIN ASSIGNMENT
SYMBOL
/OE
/CAS
DQ2
DQ3
V
SS
DQ0
DQ1
/WE
/RAS
NC
A0
A1
A2
A3
V
CC
A4
A5
A6
A7
A8
PIN DESCRIPTION
PIN
A0
–
A9
DQ0
–
DQ3
/RAS
/CAS
/OE
FUNCTION
Address Inputs
Data
Input/Output
Row Address
Strobe
Column
Address Strobe
Data Output
Enable
PIN
/WE
Vcc
Vss
NC
FUNCTION
Read/Write
Enable
Power
(+5V)
Ground
No
Connection
14
15
16
17
18
19
20
1
HANBit Electronics Co.,Ltd.
HANBit
ABSOLUTE MAXIMUM RATINGS*
SYMBOL
TA
TSTG
VIN/VOUT
VCC
IOUT
PD
PARAMETER
Ambient Temperature under Bias
Storage Temperature (Plastic)
Voltage on any Pin Relative to Vss
Power Supply Voltage
Short Circuit Output Current
Power Dissipation
RATING
0 ~ 70
-55 ~ 150
-1.0 ~ 7.0
-1.0 ~ 7.0
50
600
HMD2564Z1
UNIT
C
C
V
V
mA
mW
*NOTE:
1. Stress greater than above absolute Maximum Ratings?
May cause permanent damage to the device.
RECOMMENDED DC OPERATING CONDITIONS
(T
A
= 0 ~ 70C)
PARAMETER
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
*NOTE:
All voltages referenced to Vcc
SYMBOL
Vcc
Vss
V
IH
V
IL
MIN
4.5
0
2.4
-1.0
TYP.
5.0
0
-
-
MAX
5.5
0
Vcc+1
0.8
UNIT
V
V
V
V
DC AND OPERATING CHARACTERISTICS
SYMBOL
V
OH
V
OL
I
CC1
I
CC2
I
CC3
PARAMETER
Output High Level Voltage (IOUT = -5mA)
Output Low Level Voltage (IOUT = 4.2mA)
Operating Current
(/RAS,/CAS,Address Cycling :
tRC
=
tRC
min)
Standby Current (/RAS,/CAS = V
IH
)
/RAS Only Refresh Current
(/RAS Cycling, /CAS = V
IH
,:
tRC
=
tRC
min)
Fast Page Mode Current
I
CC4
I
CC5
I
CC6
(/RAS =V
IL
, /CAS, Address Cycling : tPC = tPC min)
Standby Current (/RAS,/CAS >= Vcc
–
0.2V)
-5
/CAS before /RAS Refresh Current (tRC =
tRC
min)
-6
Self Refresh Current
I
CCS
(/RAS=/UCAS=/LCAS=V
IL,
/WE=/OE=A0~A9= Vcc
–
0.2V or 0.2V,
DQ0~DQ31= Vcc
–
0.2V, 0.2V or Open)
Input Leakage Current
I
I(L)
I
O(L)
-5
(Any Input (0V<=V
IN
<= V
IN
+ 0.5V, All Other Pins Not Under Test = 0V)
Output Leakage Current(DOUT is Disabled, 0V<=V
OUT
<= Vcc)
-5
5
uA
5
uA
-
-
uA
75
mA
-5
-6
-5
-6
-5
-6
-
MIN
2.4
0
0.4
85
mA
75
2
85
mA
75
65
55
1
85
mA
mA
mA
mA
MAX
UNIT
V
V
2
HANBit Electronics Co.,Ltd.
HANBit
HMD2564Z1
Note: 1. Icc depends on output load condition when the device is selected.
Icc (max) is specified at the output open condition.
2. Address can be changed once or less while /RAS = V
IL.
3. Address can be changed once or less while /CAS = V
IH
CAPACITANCE
( T
A
=25 C, Vcc = 5V+/- 10%, f = 1Mhz )
SYMBOL
C
I1
C
I2
MIN
-
-
MAX
5
7
UNITS
pF
pF
NOTE
1
1,2
o
DESCRIPTION
Input Capacitance (A0-A9)
Input Capacitance (/WE,/RAS, /CAS0-
/CAS3,/OE)
Input/Output Capacitance (DQ0-31)
C
DQ1
-
7
pF
1,2
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. /CAS = VIH to disable DOUT.
AC CHARACTERISTICS
SYMBOL
t
RC
t
RWC
t
RAC
t
CAC
t
aa
t
OFF
t
T
t
RP
t
RAS
t
RSH
t
CSH
t
CAS
t
RCD
t
RAD
t
CRP
t
ASR
t
RAH
t
ASC
t
CAH
t
RAL
t
RCS
( 0 C
≤
T
A
≤
70oC , Vcc = 5V±10%, V
IH
/V
IL
= 2.4/0.8V, V
OH
/V
OL
=2.4/0.4V, See notes 1,2)
-5
-6
UNIT
MIN
MAX
MIN
110
152
50
15
25
0
3
30
50
15
50
15
20
15
5
0
10
0
10
25
0
10K
35
25
10K
12
50
0
3
40
60
15
60
15
20
15
5
0
10
0
10
30
0
10K
45
30
10K
60
15
30
12
50
MAX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
11
4
10
3,4,10
3,4,5
3,10
6
2
90
132
NOTE
o
PARAMETER
Random Read or Write Cycle Time
Read-modify-writer cycle time
Access Time from /RAS
Access Time from /CAS
Access Time from Column Address
Output Buffer Turn-off Time
Transition Time (Rise and Fall)
/RAS Precharge Time
/RAS Pulse Width
/RAS Hold Time
/CAS Hold Time
/CAS Pulse Width
/RAS to /CAS Delay Time
/RAS to Column Address Delay Time
/CAS to /RAS Precharge Time
Row Address Setup Time
Row Address Hold Time
Column Address Setup Time
Column Address Hold Time
Column Address to /RAS Lead Time
Read Command Setup Time
3
HANBit Electronics Co.,Ltd.
HANBit
t
RCH
t
RRH
t
WCH
t
WP
t
RWL
t
CWL
t
DS
t
DH
t
REF
t
wcs
t
CWD
t
RWD
t
AWD
t
CPWD
t
CSR
Read Command Hold Time to /CAS
Read Command Hold Time to /RAS
Write Command Hold Time
Write Command Pulse Width
Write Command to /RAS Lead Time
Write Command to /CAS Lead Time
Data-in Setup Time
Data-in Hold Time
Refresh Period (1024 Cycle)
Write Command Setup Time
/CAS to /WE delay time
/RAS to /WE delay time
Column Address to /WE delay time
/CAS precharge to /WE delay time
/CAS Setup Time
10
(/CAS-before-/RAS Refresh Cycle)
/CAS Hold Time
t
CHR
t
RPC
t
CPA
t
PC
t
CP
t
RASP
t
RHCP
t
OEA
t
OED
t
OEZ
t
OEH
t
RASS
t
PRS
t
CHS
Note:
cycles
before proper device operation is achieved.
10
(/CAS-before-/RAS Refresh Cycle)
/RAS Precharge to /CAS Hold Time
Access Time from /CAS Precharge
Fast Page Mode Cycle Time
Fast Page Mode /RAS Precharge Time
Fast Page Mode /CAS Pulse Time
/RAS Hold Time time from /CAS
30
Precharge
/OE Access Time
/OE to data delay
Output buffer turn off delay time from
0
/OE
/OE command hold time
/RAS Pulse Width(CBR self refresh)
/RAS Precharge Time(CBR self refresh)
/CAS Hold Time(CBR self refresh)
15
100
90
-50
15
100
110
-50
12
0
12
12
15
12
15
35
35
10
50
200K
5
30
40
10
60
200K
5
35
10
10
0
37
72
47
52
0
0
10
10
15
13
0
10
16
0
37
82
52
57
0
0
10
10
15
15
0
10
16
HMD2564Z1
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
ns
ns
ns
ns
7
7,13
7
7
7
15
9
9
8
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
16
3
12
3
1. An initial pause of 200us is required after power-up followed by any 8 /RAS-only refresh or /CAS-before-/RAS refresh
2. Input voltage levels are V
IH
/ V
IL.
V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals.
Also, transition times are measured between
.
V
IH
and V
IL
are assumed to be 5ns for all inputs.
3. Measured with a load circuit equivalent to 2TTL loads and 100pF.
4
HANBit Electronics Co.,Ltd.
HANBit
HMD2564Z1
4. Operation with the
t
RCD
(max) limit insures that
t
RAC
(max) can be met,
t
RCD
(max) is specified as a reference point only,
if
t
RCD
is greater than the specified
t
RCD
(max) limit, then access time is controlled exclusively by
t
CAC
.
5. Assumes that
t
RCD
<=
t
RCD
(max).
6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V
OH
/
V
OL .
7. T
WCS,
T
RWD,
T
CWD,
T
CPWD
are non restrictive operating parameter. They are included in the data sheet as electrical
characteristics
only. If
t
wcs
>=
t
wcs
(min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance)
throughout
the entire cycle. If
t
CWD
>=
t
CWD
(min),
t
RWD
>=
t
RWD
(min), T
CPWD
>= T
CPWD
(min), then the cycle is a read-modify-write
cycle and the data output will contain the data read from the selected address. If neither of the above conditions is
satisfied, the condition of the data out is indeterminate.
8. Either
tRCH
or
tRRH
must be satisfied for a read cycles.
9. These parameters are referenced to /CAS falling edge in early write cycles and to /WE falling edge in /OE controlled
write cycle and read-modify-write cycles.
10. Operation with the
t
RAD
(max) limit insures that
t
RAC
(max) can be met,
t
RAD
(max) is specified as a reference point only,
if
t
RAD
is greater than the specified
t
RAD
(max) limit, then access time is controlled exclusively by
t
AA
.
11.
t
ASC,
t
CAH
are are referenced to the earlier /CAS falling edge.
12.
t
CP
is specified from the later /CAS rising edge in the previous cycle to the earlier /CAS falling edge in the next cycle.
13.
t
CWD
is referenced to the later /CAS falling edge at word read-modify-write cycle.
14.
t
CWL
is specified from /WE falling edge to the earlier /CAS rising edge .
15.
t
CSR
is referenced to the earlier /CAS falling edge before /RAS transition low.
16.
t
CHR
is referenced to the later /CAS rising edge after /RAS transition low.
PACKAGING INFORMATION
5
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