HANBit
HMD16M36M12EG
64Mbyte (16Mx36) EDO/with Parity Mode 4K Ref. 72pin-SIMM Design
Part No. HMD16M36M12EG
GENERAL DESCRIPTION
The HMD16M36M12EG is a 16M x 36bit dynamic RAM high-density memory module. The module consists of eight
CMOS 16M x 4bit DRAMs in 32-pin SOJ or TSOP packages and four CMOS 16Mx1bit DRAMs in SOJ or TSOP packages
mounted on a 72-pin glass-epoxy substrate. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board
for each DRAM components. The module is a Single In-line Memory Module with edge connections and is intended for
mounting in to 72-pin edge connector sockets. All module components may be powered from a single 5V DC power supply
and all inputs and outputs are TTL-compatible.
FEATURES
wPart
Identification
HMD16M36M12EG
---4K Cycles/64ms Ref, Gold
w
Access times : 50, 60ns
w
High-density 64MByte design
w
Single + 5V
±0.5V
power supply
w
JEDEC standard Pdpin & pinout
w
TTL compatible inputs and outputs
w/CAS-before-/RAS
& Hidden Refresh capability
w/RAS-only
refresh capability
wEDO
Mode Operation
PIN
1
2
3
4
5
6
7
8
9
10
SYMBOL
Vss
DQ0
DQ18
DQ1
DQ19
DQ2
DQ20
DQ3
DQ21
Vcc
NC
A0
A1
A2
A3
A4
A5
A6
A10
DQ4
DQ22
DQ5
DQ23
DQ6
PIN
PIN
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
ASSIGNMENT
SYMBOL
DQ24
DQ7
DQ25
A7
A11
Vcc
A8
A9
NC
/RAS2
DQ26
DQ8
DQ17
DQ35
Vss
/CAS0
/CAS2
/CAS3
/CAS1
/RAS0
NC
NC
/WE
NC
PIN
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
SYMBOL
DQ9
DQ27
DQ10
DQ28
DQ11
DQ29
DQ12
DQ30
DQ13
DQ31
Vcc
DQ32
DQ14
DQ33
DQ15
DQ34
DQ16
NC
PD1
PD2
PD3
PD4
NC
Vss
OPTIONS
w
Timing
50ns access
60ns access
w
Packages
72-pin SIMM
MARKING
-5
-6
M
11
12
13
14
15
16
17
18
PERFORMANCE RANGE
Speed
5
6
t
RAC
50ns
60ns
t
CAC
13ns
15ns
t
RC
90ns
110ns
19
20
21
22
PRESENCE DETECT PINS
(Optional)
Pin
PD1
PD2
PD3
PD4
50ns
Vss
NC
Vss
Vss
60ns
Vss
23
24
72PIN SIMM TOP
NC
NC
NC
VIEW
URL:www.hbe.co.kr
REV.1.0(August.2002)
HANBit Electronics Co.,Ltd.
-1-
HANBit
FUNCTIONAL BLOCK DIAGRAM
HMD16M36M12EG
DQ0-DQ35
/CAS0
/RAS0
CAS
CAS
RAS
RAS
OE
WE
U1
U0
DQ0
DQ0-DQ3
DQ1
OE
W
A0-A11
A0-A11
DQ2
DQ3
DQ0
/CAS2
/RAS2
CAS
RAS
OE WE
U7
DQ18-DQ21
A0-A11
CAS
CAS
RAS
RAS
OE
WE
U2
U1
DQ4-DQ7
DQ1
OE
W
A0-A11
A0-A11
DQ2
DQ3
D
DQ8
Q
CAS
RAS
OE WE
U8
DQ22-DQ25
A0-A11
CAS
CAS
RAS WE
RAS W
U2
U10
A0-A11
A0-A11
CAS
RAS
U3
WE
DQ26
A0-A11
/CAS1
CAS
CAS
RAS
RAS
OE
WE
U5
U0
DQ0
DQ9-DQ12
DQ1
OE
W
A0-A11
A0-A11
DQ2
DQ3
DQ0
/CAS3
CAS
RAS
OE WE
U11
DQ27-DQ30
A0-A11
CAS
CAS
RAS
RAS
OE
WE
U1
U6
DQ13-DQ16
DQ1
OE
W
A0-A11
A0-A11
DQ2
DQ3
D
DQ17
Q
CAS
RAS
OE WE
U12
DQ31-DQ34
A0-A11
CAS
CAS
RAS WE
RAS W
U2
U9
A0-A11
A0-A11
CAS
RAS
U4
WE
DQ35
A0-A11
/WE
A0-A11
URL:www.hbe.co.kr
REV.1.0(August.2002)
HANBit Electronics Co.,Ltd.
-2-
HANBit
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Power Dissipation
Storage Temperature
SYMBOL
V
IN ,OUT
Vcc
P
D
T
STG
HMD16M36M12EG
RATING
-1V to 7.0V
-1V to 7.0V
12W
-55oC to 125oC
Short Circuit Output Current
I
OS
50mA
w
Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
( Voltage reference to V
SS
, TA=0 to 70 o C )
PARAMETER
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
SYMBOL
Vcc
Vss
V
IH
V
IL
MIN
4.5
0
2.4
-1.0
TYP.
5.0
0
-
-
MAX
5.5
0
Vcc
0.8
UNIT
V
V
V
V
DC AND OPERATING CHARACTERISTICS
SYMBOL
I
CC1
-6
I
CC2
I
CC3
-6
-5
I
CC4
-6
I
CC5
I
CC6
-6
I
l(L)
I
O(L)
V
OH
V
OL
I
CC1
: Operating Current * (/RAS , /CAS , Address cycling @t
RC
=min.)
URL:www.hbe.co.kr
REV.1.0(August.2002)
HANBit Electronics Co.,Ltd.
SPEED
-5
MIN
-
-
-
-
-
-
-
-
-
-
-10
MAX
1080
960
24
1080
960
840
600
12
1080
960
10
5
2.4
-
-
0.4
UNITS
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
V
V
Don’t care
-5
Don’t care
-5
Don’t care
-5
-3-
HANBit
I
CC2
: Standby Current ( /RAS=/CAS=V
IH
)
I
CC3
: /RAS Only Refresh Current * ( /CAS=V
IH
, /RAS, Address cycling @t
RC
=min )
I
CC4
: Fast Page Mode Current * (/RAS=V
IL
, /CAS, Address cycling @t
PC
=min )
I
CC5
: Standby Current (/RAS=/CAS=Vcc-0.2V )
I
CC6
: /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t
RC
=min )
HMD16M36M12EG
I
IL
: Input Leakage Current (Any input 0V
≤
V
IN
≤
6.5V, all other pins not under test = 0V)
I
OL
: Output Leakage Current (Data out is disabled, 0V
≤
V
OUT
≤
5.5V
V
OH
: Output High Voltage Level (I
OH
= -5mA )
V
OL
: Output Low Voltage Level (I
OL
= 4.2mA )
*
NOTE:
I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the
output open. I
CC
is specified as an average current. In I
CC1
and I
CC3
, address cad be changed maximum once
while /RAS=V
IL
. In I
CC4
, address can be changed maximum once within one page mode cycle.
CAPACITANCE
( T
A
=25 C, Vcc = 5V, f = 1Mz )
SYMBOL
C
IN1
C
IN2
C
IN3
C
IN4
C
DQ1
MIN
-
-
-
-
-
MAX
50
66
38
24
17
UNITS
pF
pF
pF
pF
pF
o
DESCRIPTION
Input Capacitance (A0-A11)
Input Capacitance (/W)
Input Capacitance (/RAS0)
Input Capacitance (/CAS0-/CAS3)
Input/Output Capacitance (DQ0-31)
AC CHARACTERISTICS
PARAMETER
Random read or write cycle time
Access time from /RAS
Access time from /CAS
Access time from column address
/CAS to output in Low-Z
Output buffer turn-off delay
Transition time (rise and fall)
/RAS precharge time
/RAS pulse width
/RAS hold time
/CAS hold time
/CAS pulse width
/RAS to /CAS delay time
( 0 C
≤
T
A
≤
70oC , Vcc = 5V±10%, See notes 1,2.)
-5
SYMBOL
MIN
t
RC
t
RAC
t
CAC
t
AA
t
CLZ
t
OFF
t
T
t
RP
t
RAS
t
RSH
t
CSH
t
CAS
t
RCD
3
3
1
30
50
13
38
8
20
10K
37
10K
13
50
84
50
13
25
3
3
1
40
60
15
45
10
20
10K
45
10K
15
50
MAX
MIN
104
60
15
30
MAX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-6
UNIT
o
URL:www.hbe.co.kr
REV.1.0(August.2002)
HANBit Electronics Co.,Ltd.
-4-
HANBit
/RAS to column address delay time
/CAS to /RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address hold referenced to /RAS
Column Address to /RAS lead time
Read command set-up time
Read command hold referenced to /CAS
Read command hold referenced to /RAS
Write command hold time
Write command hold referenced to /RAS
Write command pulse width
Write command to /RAS lead time
Write command to /CAS lead time
Data-in set-up time
Data-in hold time
Data-in hold referenced to /RAS
Refresh period
Write command set-up time
/CAS setup time (C-B-R refresh)
/CAS hold time (C-B-R refresh)
/RAS precharge to /CAS hold time
Access time from /CAS precharge
Fast page mode cycle time
/CAS precharge time (Fast page)
/RAS pulse width (Fast page )
/W to /RAS precharge time(C-B-R refresh)
/W to /RAS hold time (C-B-R refresh)
/CAS precharge(C-B-R counter test)
t
RAD
t
CRP
t
ASR
t
RAH
t
ASC
t
CAH
t
AR
t
RAL
t
RCS
t
RCH
t
RRH
t
WCH
t
WCR
t
WP
t
RWL
t
CWL
t
DS
t
DH
t
DHR
t
REF
t
WCS
t
CSR
t
CHR
t
RPC
t
CPA
t
PC
t
CP
t
RASP
t
WRP
t
WRH
t
CPT
40
8
50
10
10
20
200K
0
5
10
5
28
45
10
60
10
10
30
15
5
0
10
0
8
50
25
0
0
0
10
50
10
13
8
0
8
50
64
0
5
10
5
25
15
5
0
10
0
10
55
30
0
0
0
10
55
10
10
10
0
10
55
HMD16M36M12EG
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
64
ns
ns
ns
ns
ns
35
ns
ns
ns
200K
ns
ns
ns
ns
NOTES
1.
An initial pause of 200µs is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.
V
IH (min)
and V
IL (max)
are reference levels for measuring timing of input signals. Transition times are measured between
V
IH(min)
and V
IL(max)
and are assumed to be 5ns for all inputs.
3.
Measured with a load equivalent to 2TTL loads and 100pF
4.
Operation within the t
RCD(max)
limit insures that t
RAC(max)
can be met. t
RCD(max)
is specified as a reference point only. If t
RCD
URL:www.hbe.co.kr
REV.1.0(August.2002)
HANBit Electronics Co.,Ltd.
-5-
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