ALDEC 8051 IP Core Data Sheet
April 11, 2006 (version 1.0)
Overview
The 8051 core is the HDL model of the Intel™ 8-bit 8051 micro controller. The model is fully
compatible with the Intel 8051 standard.
Features
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Opcode and Cycle Equivalent to Intel standard 8051
Support for Intel Hex file format
Up to 4K Bytes Internal Program Memory (ROM)
Up to 128 Bytes Internal Data Memory (RAM)
Up to 64K Bytes External Program Memory address space
Up to 64K Bytes External Data Memory address space
Up to 128 Special Function Registers (SFR)
32 bi-directional and individually addressable I/O Lines
Two 16-bit timer/counters
Full Duplex UART (Serial Port)
6-Source/5-Vector Interrupt Structure with Two Priority Levels
Pinout
Table 1:
Core Signal Pinout
Name
CLK
1)
EA
2)
RST
2)
ALE
2)
PSEN
2)
P0[7:0]
3)
P1[7:0]
3)
P2[7:0]
3)
P3[7:0]
3)
Direction
Input
Input
Input
Output
Output
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Polarity
-
Low
High
High
Low
-
-
-
-
Clock input
External Access
Synchronous reset
Address Latch Enable
Program Store Enable
Port P0
Port P1
Port P2
Port P3
Description
Notes:
1) XTAL1 and XTAL2 original device pins were replaced with one CLK (clock) input
signal. The clock frequency value has no limitations during the functional simulation.
2) EA, RST, ALE and PSEN signals behave exactly the same as the original device and
are compatible with the Intel 8051 standard.
3) In the synthesizable model, each bidirectional pin is defined in the core interface as
two separated VHDL ports. Optionally, using the Aldec VHDL/Verilog Interface, it can
be merged to one bidirectional VHDL port. The behavioral model has bidirectional
ports.
www.aldec.com
©2006 Aldec, Inc. All rights reserved
Aldec 8051 Core Data Sheet
Deliverables
Available at No Cost:
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Verilog and/or VHDL Simulation Model (Encrypted for Aldec simulator only)
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Data Sheet
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Application Notes
Available Upon ordering:
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VHDL/Verilog source code
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Internal program memory
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ROM Generator tool
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RAM memory
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Technology-dependent EDIF and VHDL/Verilog netlists
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Aldec 8051 VHDL/Verilog Interface
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Verification Test Bench source code
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RTL Source compilation and simulation scripts
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Synthesis scripts
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Integration Manual
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User-Guide
Ordering
Information
Aldec, Inc.
2260 Corporate Circle
Henderson, NV 89074
Tel: 702-990-4400
Fax: 702-990-4414
Email:
ipcores@aldec.com
http://www.aldec.com
www.aldec.com
©2006 Aldec, Inc. All rights reserved
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