HANBit
HMD2M32M4E/4EG
8Mbyte(2Mx32) EDO Mode, 1K Refresh 72Pin SIMM, 5V Design
Part No. HMD2M32M4E, HMD2M32M4EG
GENERAL DESCRIPTION
The HMD2M32M4E is a 2M x 32bit dynamic RAM high-density memory module. The module consists of four CMOS 1M
x 16bit DRAMs in 42-pin SOJ packages mounted on a 72 -pin, double-sided, FR-4-printed circuit board.
A 0.1 or 0.22uF
decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a single In -line
Memory Module with edge connections and is intended for mounting in to 72 -pin edge connector sockets. All module
components may be powered from a single 5V DC power supply and all inputs and outputs are TTL -compatible.
FEATURES
w
Part Identification
HMD2M32M4E---- 1024 Cycles/16ms Ref . Solder
HMD2M32M4EG- -1024 Cycles/16ms Ref . Gold
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Access times : 50, 60ns
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High-density 8MByte design
w
Single + 5V
±0.5V
power supply
w
JEDEC standard pinout
w
EDO mode operation
w
TTL compatible inputs and outputs
w
FR4-PCB design
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
tRC
90ns
110ns
130ns
19
20
21
22
23
24
60ns
NC
NC
NC
NC
PIN
SYMBOL
Vss
DQ0
DQ16
DQ1
DQ17
DQ2
DQ18
DQ3
DQ19
Vcc
NC
A0
A1
A2
A3
A4
A5
A6
A10
DQ4
DQ20
DQ5
DQ21
DQ6
70ns
NC
NC
Vss
NC
ASSIGNMENT
PIN
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
SYMBOL
DQ22
DQ7
DQ23
A7
A11
Vcc
A8
A9
/RAS3
/RAS2
NC
NC
NC
NC
Vss
/CAS0
/CAS2
/CAS3
/CAS1
/RAS0
/RAS1
NC
/WE
NC
PIN
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
SYMBOL
DQ8
DQ24
DQ9
DQ25
DQ10
DQ26
DQ11
DQ27
DQ12
DQ28
Vcc
DQ29
DQ13
DQ30
DQ14
DQ31
DQ15
NC
PD1
PD2
PD3
PD4
NC
Vss
OPTIONS
w
Timing
50ns access
60ns access
70ns access
w
Packages
72-pin SIMM
MARKING
-50
-60
-70
M
PERFORMANCE RANGE
Speed
5
6
7
tRAC
50ns
60ns
70ns
tCAC
15ns
15ns
15ns
PRESENCE DETECT PINS
Pin
PD1
PD2
PD3
PD4
50ns
NC
NC
Vss
Vss
URL:www.hbe.co.kr
REV.1.0 (August.2002)
6
HANBit Electronics Co.,Ltd.
HANBit
Functional Block Diagram
HMD2M32M4E/4EG
U2
DQ1
/RAS0
/CAS0
/CAS1
/RAS
/LCAS
/UCAS
/OE
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
A0-A11
DQ0
DQ0-15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
U4
/RAS
LCAS
/UCAS
/OE
/RAS1
/CAS0
/CAS1
/W
/W
A0-A11
U1
/RAS2
/CAS2
/CAS3
/RAS
/LCAS
/UCAS
/OE
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ16-31
DQ11
DQ12
DQ13
DQ14
DQ15
/W
U3
/RAS
/RAS3
/CAS2
/CAS3
/LCAS
/UCAS
/OE
/W
A0-A11
A0-A11
/WE
A0-A11
Vcc
Vss
0.1uFor
0.22uF
Capacitor
for each DRAM
To all DRAMs
URL:www.hbe.co.kr
REV.1.0 (August.2002)
7
HANBit Electronics Co.,Ltd.
HANBit
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Power Dissipation
Storage Temperature
SYMBOL
V
IN ,OUT
Vcc
P
D
T
STG
HMD2M32M4E/4EG
RATING
-1V to 7.0V
-1V to 7.0V
4W
-55oC to 150oC
Short Circuit Output Current
I
OS
50mA
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Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(Voltage reference to V
SS
, TA=0 to 70 o C )
PARAMETER
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
SYMBOL
Vcc
Vss
V
IH
V
IL
MIN
4.5
0
2.4
-1.0
TYP
5.0
0
-
-
MAX
5.5
0
Vcc+1
0.8
UNIT
V
V
V
V
DC AND OPERATING CHARACTERISTICS
SYMBOL
I
CC1
I
CC2
I
CC3
-5
-6
-5
-6
SPEED
-5
-6
MIN
-
-
-
-
-
-
-
-
-5
-6
I
l(L)
I
O(L)
V
OH
V
OL
I
CC1
: Operating Current * (/RAS , /CAS , Address cycling
I
CC2
: Standby Current ( /RAS=/CAS=V
IH
)
I
CC3
: /RAS Only Refresh Current * ( /CAS=V
IH
, /RAS, Address cycling @t
RC
=min )
URL:www.hbe.co.kr
REV.1.0 (August.2002)
MAX
305
284
8
304
284
244
224
4
304
284
20
10
-
0.4
UNITS
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
I
CC4
I
CC5
I
CC6
-
-
-20
-10
2.4
-
@t
RC
=min.)
8
HANBit Electronics Co.,Ltd.
HANBit
I
CC4
: Fast Page Mode Current * (/RAS=V
IL
, /CAS, Address cycling @t
PC
=min )
I
CC5
: Standby Current (/RAS=/CAS=Vcc-0.2V )
I
CC6
: /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t
RC
=min )
HMD2M32M4E/4EG
I
IL
: Input Leakage Current (Any input 0V
£
V
IN
£
6.5V, all other pins not under test = 0V)
I
OL
: Output Leakage Current (Data out is disabled, 0V
£
V
OUT
£
5.5V
V
OH
: Output High Voltage Level (I
OH
= -5mA )
V
OL
: Output Low Voltage Level (I
OL
= 4.2mA )
*
NOTE:
I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained wi th the
output open. I
CC
is specified as an average current. In I
CC1
and I
CC3
, address cad be changed maximum once
while /RAS=V
IL
. In I
CC4
, address can be changed maximum once within one page mode cycle.
CAPACITANCE
( T
A
=25 C, Vcc = 5V, f = 1Mz )
SYMBOL
C
IN1
C
IN2
C
IN3
C
IN4
C
DQ1
o
o
DESCRIPTION
Input Capacitance (A0-A10)
Input Capacitance (/W)
Input Capacitance (/RAS0)
Input Capacitance (/CAS0-/CAS3)
Input/Output Capacitance (DQ0-31)
MIN
-
-
-
-
-
MAX
44
48
40
29
29
UNITS
pF
pF
pF
pF
pF
AC CHARACTERISTICS
( 0 C
£
T
A
£
70oC , Vcc = 5V±10%, See notes 1,2.)
-5
MIN
90
50
15
25
3
3
2
30
50
13
40
8
20
15
5
0
10
10K
37
25
10K
13
50
3
3
2
40
60
17
50
10
20
15
5
0
10
10K
45
30
10K
15
50
MAX
MIN
110
60
17
30
-6
MAX
STANDARD OPERATION
Random read or write cycle time
Access time from /RAS
Access time from /CAS
Access time from column address
/CAS to output in Low-Z
Output buffer turn-off delay
Transition time (rise and fall)
/RAS precharge time
/RAS pulse width
/RAS hold time
/CAS hold time
/CAS pulse width
/RAS to /CAS delay time
/RAS to column address delay time
/CAS to /RAS precharge time
Row address set-up time
Row address hold time
URL:www.hbe.co.kr
REV.1.0 (August.2002)
SYMBOL
t
RC
t
RAC
t
CAC
t
AA
t
CLZ
t
OFF
t
T
t
RP
t
RAS
t
RSH
t
CSH
t
CAS
t
RCD
t
RAD
t
CRP
t
ASR
t
RAH
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9
HANBit Electronics Co.,Ltd.
HANBit
Column address set-up time
Column address hold time
Column Address to /RAS lead time
Read command set-up time
Read command hold referenced to /CAS
Read command hold referenced to /RAS
Write command hold time
Write command pulse width
Write command to /RAS lead time
Write command to /CAS lead time
Data-in set-up time
Data-in hold time
Refresh period
(1K Ref. Normal)
t
ASC
t
CAH
t
RAL
t
RCS
t
RCH
t
RRH
t
WCH
t
WP
t
RWL
t
CWL
t
DS
t
DH
t
REF
t
WCS
t
CSR
t
CHR
t
RPC
t
CPA
t
CP
t
RASP
t
WRP
t
WRH
8
50
10
10
0
5
10
5
0
8
25
0
0
0
10
10
13
13
0
8
HMD2M32M4E/4EG
0
10
30
0
0
0
10
10
15
15
0
10
16
0
5
10
5
30
10
200K
60
10
10
200K
35
16
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write command set-up time
/CAS setup time (C-B-R refresh)
/CAS hold time (C-B-R refresh)
/RAS precharge to /CAS hold time
Access time from /CAS precharge
/CAS precharge time (Fast page)
/RAS pulse width (Fast page )
/W to /RAS precharge time (C-B-R refresh)
/W to /RAS hold time (C-B-R refresh)
NOTES
1.
An initial pause of 200ms is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.
V
IH (min)
and V
IL (max)
are reference levels for measuring timing of input signals. Transition times are measured between
V
IH(min)
and V
IL(max)
and are assumed to be 5ns for all inputs.
3.
Measured with a load equivalent to 2TTL loads and 100pF
4.
Operation within the t
RCD(max)
limit insures that t
RAC(max)
can be met. t
RCD(max)
is specified as a reference point only. If t
RCD
is greater than the specified t
RCD(max)
limit, then access time is controlled exclusively by t
CAC
.
5.
Assumes that t
RCD
³
t
RCD(max)
6. t
AR
, t
WCR
, t
DHR
are referenced to t
RAD(max)
7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V
OH
or V
OL
.
8. t
WCS
, t
RWD
, t
CWD
and t
AWD
are non restrictive operating parameter.
They are included in the data sheet as e lectrical characteristic only. If t
WCS
³
tWCS(min)
the cycle is an early write
cycle and the data out pin will remain high impedance for the duration of the cycle.
9. Either t
RCH
or t
RRH
must be satisfied for a read cycle.
10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in read -
write cycles.
11. Operation within the t
RAD(max)
limit insures that t
RAC(max)
can be met. t
RAD(max)
is specified as a reference
point only. If t
RAD
is greater than the specified t
RAD(max)
limit. then access time is controlled by t
AA
.
URL:www.hbe.co.kr
REV.1.0 (August.2002)
10
HANBit Electronics Co.,Ltd.
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