HANBit
HMD1M36M3EG
4Mbyte(1Mx36) 72-pin SIMM EDO with Parity MODE, 1K Ref. 5V
Part No. HMD1M36M3EG
GENERAL DESCRIPTION
The HMD1M36M3EG is a 1M x 36 bit dynamic RAM high-density memory module. The module consists of two CMOS
1M x 16 bit DRAMs in 42-pin TSOP packages and one CMOS 1M x 4bit Quad CAS DRAM in 28pin SOJ package
mounted on a 72-pin. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM
components. The module is a single In-line memory module with edge connections and is intended for mounting in to 72-
pin edge connector sockets. All module components may be powered from a single 5V DC power supply. All inputs and
outputs are TTL-compatible.
FEATURES
w
Part Identification
HMD1M36M3EG- 1K Cycles/16ms Ref, Gold
w
Access times : 50, 60ns
w
High-density 4MByte design
w
Single +5V
±0.5V
power supply
wJEDEC
standard pinout
w
EDO Mode operation
w
TTL compatible inputs and outputs
w
FR4-PCB design
PIN
1
2
3
4
5
6
7
8
9
PIN ASSIGNMENT
SYMBOL
Vss
DQ0
DQ18
DQ1
DQ19
DQ2
DQ20
DQ3
DQ21
Vcc
NC
A0
A1
A2
A3
A4
A5
A6
NC
DQ4
DQ22
DQ5
DQ23
DQ6
PIN
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
SYMBOL
DQ24
DQ7
DQ25
A7
NC
Vcc
A8
A9
NC
/RAS0
DQ26
DQ8
DQ17
DQ35
Vss
/CAS0
/CAS2
/CAS3
/CAS1
/RAS0
NC
NC
/WE
NC
PIN
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
SYMBOL
DQ9
DQ27
DQ10
DQ28
DQ11
DQ29
DQ12
DQ30
DQ13
DQ31
Vcc
DQ32
DQ14
DQ33
DQ15
DQ34
DQ16
NC
PD1
PD2
PD3
PD4
NC
Vss
OPTIONS
w
Timing
50ns access
60ns access
w
Packages
72-pin SIMM
MARKING
-5
-6
M
10
11
12
13
14
15
16
17
PRESENCE DETECT PINS
Pin
PD1
PD2
PD3
PD4
50ns
Vss
NC
Vss
Vss
60ns
Vss
NC
NC
NC
18
19
20
21
22
23
24
PERFORMANCE RANGE
Speed
5
6
tRAC
50ns
60ns
tCAC
13ns
15ns
tRC
90ns
110ns
tHPC
26ns
30ns
URL:www.hbe.co.kr
REV.1.0(August.2002)
1
HANBit Electronics Co.,Ltd.
HANBit
HMD1M36M3EG
FUNCTIONAL BLOCK DIAGRAM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U0
/RAS0
/CAS0
/CAS1
/RAS
/LCAS
DQ0-DQ7
/UCAS
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
A0-A11
DQ16
/OE
DQ9-DQ16
/W
/RAS
/CAS0
/CAS1
/CAS2
/CAS3
/W
U1
DQ0
DQ1
DQ2
DQ3
A0-A11
DQ8
DQ17
DQ26
DQ35
U2
/RAS
/CAS2
/LCAS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ18-DQ25
/CAS3
/UCAS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
A0-A11
DQ15
/OE
W
DQ27-DQ34
/W
A0-A11
Vcc
URL:www.hbe.co.kr
REV.1.0(August.2002)
0.1uF
or
0.22uF To all DRAMs
Capacitor
for each DRAM
HANBit Electronics Co.,Ltd.
2
HANBit
HMD1M36M3EG
Absolute Maximum Ratings
PARAMETER
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Power Dissipation
Storage Temperature
Vss
SYMBOL
V
IN ,OUT
Vcc
P
D
T
STG
RATING
-1V to 7.0V
-1V to 7.0V
9W
-55oC to 150oC
Short Circuit Output Current
I
OS
50mA
w
Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
( Voltage reference to V
SS
, TA=0 to 70 o C )
PARAMETER
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
SYMBOL
Vcc
Vss
V
IH
V
IL
MIN
4.5
0
2.4
-1.0
TYP.
5.0
0
-
-
MAX
5.5
0
Vcc+1
0.8
UNIT
V
V
V
V
DC AND OPERATING CHARACTERISTICS
SYMBOL
I
CC1
-6
I
CC2
-5
I
CC3
-6
-5
I
CC4
-6
I
CC5
-5
I
CC6
-6
I
l(L)
I
O(L)
V
OH
V
OL
I
CC1
: Operating Current * (/RAS , /CAS , Address cycling @t
RC
=min.)
URL:www.hbe.co.kr
REV.1.0(August.2002)
SPEED
-5
MIN
-
-
-
-
-
-
-
-
-
-
-40
-5
2.4
-
MAX
990
900
18
990
900
990
900
9
990
900
45
5
-
0.4
UNITS
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
V
V
HANBit Electronics Co.,Ltd.
3
HANBit
I
CC2
: Standby Current ( /RAS=/CAS=V
IH
)
I
CC3
: /RAS Only Refresh Current * ( /CAS=V
IH
, /RAS, Address cycling @t
RC
=min )
I
CC4
: Fast Page Mode Current * (/RAS=V
IL
, /CAS, Address cycling @t
PC
=min )
I
CC5
: Standby Current (/RAS=/CAS=Vcc-0.2V )
I
CC6
: /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t
RC
=min )
I
IL
: Input Leakage Current (Any input 0V
≤
V
IN
≤
6.5V, all other pins not under test = 0V)
I
OL
: Output Leakage Current (Data out is disabled, 0V
≤
V
OUT
≤
5.5V
V
OH
: Output High Voltage Level (I
OH
= -5mA )
V
OL
: Output Low Voltage Level (I
OL
= 4.2mA )
HMD1M36M3EG
*
NOTE:
I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the
output open. I
CC
is specified as an average current. In I
CC1
and I
CC3
, address cad be changed maximum once
while /RAS=V
IL
. In I
CC4
, address can be changed maximum once within one page mode cycle.
o
CAPACITANCE
( T
A
=25 C, Vcc = 5V, f = 1Mz )
SYMBOL
C
IN1
C
IN2
C
IN3
C
IN4
C
DQ1
MIN
-
-
-
-
-
MAX
65
80
50
40
20
UNITS
pF
pF
pF
pF
pF
DESCRIPTION
Input Capacitance (A0-A10)
Input Capacitance (/W)
Input Capacitance (/RAS0)
Input Capacitance (/CAS0-/CAS3)
Input/Output Capacitance (DQ0-31)
AC CHARACTERISTICS
( 0 C
≤
T
A
≤
70oC , Vcc = 5V±10%, See notes 1,2.)
-5
-6
UNIT
MIN
MAX
MIN
110
50
13
25
3
3
2
30
50
13
38
8
20
15
10K
37
25
10K
13
50
3
3
2
40
60
15
45
10
20
15
10K
45
30
10K
15
50
60
15
30
MAX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
90
o
STANDARD OPERATION
Random read or write cycle time
Access time from /RAS
Access time from /CAS
Access time from column address
/CAS to output in Low-Z
Output buffer turn-off delay
Transition time (rise and fall)
/RAS precharge time
/RAS pulse width
/RAS hold time
/CAS hold time
/CAS pulse width
/RAS to /CAS delay time
/RAS to column address delay time
SYMBOL
t
RC
t
RAC
t
CAC
t
AA
t
CLZ
t
OFF
t
T
t
RP
t
RAS
t
RSH
t
CSH
t
CAS
t
RCD
t
RAD
URL:www.hbe.co.kr
REV.1.0(August.2002)
4
HANBit Electronics Co.,Ltd.
HANBit
/CAS to /RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column Address to /RAS lead time
Read command set-up time
Read command hold referenced to /CAS
Read command hold referenced to /RAS
Write command hold time
Write command hold referenced to /RAS
Write command pulse width
Write command to /RAS lead time
Write command to /CAS lead time
Data-in set-up time
Data-in hold time
Data-in hold referenced to /RAS
Refresh period
Write command set-up time
/CAS setup time (C-B-R refresh)
/CAS hold time (C-B-R refresh)
/RAS precharge to /CAS hold time
Access time from /CAS precharge
Fast page mode cycle time
/CAS precharge time (Fast page)
/RAS pulse width (Fast page )
/W to /RAS precharge time (C-B-R refresh)
/W to /RAS hold time (C-B-R refresh)
/CAS precharge(C-B-R counter test)
NOTES
t
CRP
t
ASR
t
RAH
t
ASC
t
CAH
t
RAL
t
RCS
t
RCH
t
RRH
t
WCH
t
WCR
t
WP
t
RWL
t
CWL
t
DS
t
DH
t
DHR
t
REF
t
WCS
t
CSR
t
CHR
t
RPC
t
CPA
t
PC
t
CP
t
RASP
t
WRP
t
WRH
t
CPT
40
8
50
10
10
20
200K
0
5
10
5
30
5
0
10
0
8
25
0
0
0
10
50
10
13
8
0
8
50
64
HMD1M36M3EG
5
0
10
0
10
30
0
0
0
10
50
10
15
10
0
10
50
64
0
5
10
5
35
40
10
60
10
10
20
200K
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.
An initial pause of 200µs is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.
V
IH (min)
and V
IL (max)
are reference levels for measuring timing of input signals. Transition times are measured between
V
IH(min)
and V
IL(max)
and are assumed to be 5ns for all inputs.
3.
Measured with a load equivalent to 2TTL loads and 100pF
4.
Operation within the t
RCD(max)
limit insures that t
RAC(max)
can be met. t
RCD(max)
is specified as a reference point only. If t
RCD
is greater than the specified t
RCD(max)
limit, then access time is controlled exclusively by t
CAC
.
5.
Assumes that t
RCD
≥
t
RCD(max)
6. t
AR
, t
WCR
, t
DHR
are referenced to t
RAD(max)
URL:www.hbe.co.kr
REV.1.0(August.2002)
5
HANBit Electronics Co.,Ltd.
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