3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
256 x 256
FEATURES:
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IDT72V70190
256 x 256 channel non-blocking switching at 2.048 Mb/s
Per-channel variable or constant throughput delay
Automatic identification of ST-BUS
®
/GCI interfaces
Accept 8 serial data streams of 2.048 Mb/s
Automatic frame offset delay measurement
Per-stream frame delay offset programming
Per-channel high impedance output control
Per-channel Processor Mode
Control interface compatible to Intel/Motorola CPUs
Connection memory block programming
Available in 64-pin Thin Plastic Quad Flatpack (TQFP) and
64-pin Small Thin Quad Flatpack (STQFP)
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·
3.3V Power Supply
•
Operating Temperature Range -40°C to +85°C
°
°
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3.3V I/O with 5V Tolerant Inputs
DESCRIPTION:
The IDT72V70190 is a non-blocking digital switch that has a capacity of
256 x 256 channels at 2.048 Mb/s. Some of the main features are: program-
mable stream and channel control, Processor Mode, input offset delay and high-
impedance output control.
Per-stream input delay control is provided for managing large multi-chip
switches that transport both voice channel and concatenated data channels. In
addition, input streams can be individually calibrated for input frame offset.
FUNCTIONAL BLOCK DIAGRAM
V
CC
GND
RESET
ODE
Loopback
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
TX0
Receive
Serial Data
Streams
Data Memory
Output
MUX
Transmit
Serial Data
Streams
Connection
Memory
TX1
TX2
TX3
TX4
TX5
Internal
Registers
TX6
TX7
Timing Unit
Microprocessor Interface
CLK
F0i
FE
IC
AS/ IM DS/
RD
ALE
CS
R/W/ A0-A7
DTA
D8-D15/
WR
AD0-AD7
CCO
5717 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS
is a trademark of Mitel Corp.
MARCH 2003
DSC-5717/4
1
2003
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT72V70190 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 256 x 256
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
GND
GND
CCO
ODE
VCC
DTA
51
TX7
TX6
TX5
TX4
TX3
TX2
TX1
TX0
D15
50
PIN 1
64
63
62
61
57
56
55
54
59
58
53
52
60
49
GND
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
F0i
FE
GND
CLK
VCC
DNC
DNC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
29
30
17
18
19
20
24
25
26
27
22
23
28
31
21
32
D14
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
D13
D12
D11
D10
D9
D8
GND
VCC
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
R/W/RW
AS/ALE
RESET
DS/RD
GND
CS
A0
A3
A4
A2
A1
A5
A6
A7
IM
IC
5717 drw02
TQFP 0.80 pitch, 14mm x 14mm (PN64-1, order code: PF)
STQFP 0.50 pitch, 10mm x 10mm (PP64-1, order code: TF)
TOP VIEW
NOTES:
1. DNC - Do Not Connect.
2. All I/O pins are 5V tolerant.
3. IC - Internal Connection, tie to Ground for normal operation.
2
IDT72V70190 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 256 x 256
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
SYMBOL
GND
Vcc
TX0-7
RX0-7
F0i
FE
CLK
RESET
NAME
Ground.
Vcc
TX Output 0 to 7
(Three-state Outputs)
RX Input 0 to 7
Frame Pulse
Frame Evaluation
Clock
Device Reset
(Schmitt Trigger Input)
I/O
DESCRIPTION
Ground Rail.
+3.3 Volt Power Supply.
Serial data output stream. These streams have a data rate of 2.048 Mb/s.
Serial data input stream. These streams have a data rate of 2.048 Mb/s.
This input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS
®
and GCI specifications.
This pin is the frame measurement input.
Serial clock for shifting data in/out on the serial streams (RX/TX 0-7). This input accepts a 4.096 MHz clock.
This input (active LOW) puts the IDT72V70190 in its reset state that clears the device internal counters, registers
and brings TX0-7 and microport data outputs to a high-impedance state. The time constant for a power up
reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the
RESET
pin must be held LOW for a minimum of 100ns to reset the device.
When non-multiplexed CPU bus operation is selected, these lines provide the A0-A7 address lines to the internal
memories.
For Motorola multiplexed bus operation, this input is DS. This active HIGH DS input works in conjunction with
CS
to enable the read and write operations. For Motorola non-multiplexed CPU bus operation, this input is DS.
This active LOW input works in conjunction with
CS
to enable the read and write operations. For Intel multiplexed
bus operation, this input is
RD.
This active LOW input sets the data bus lines (AD0-7, D8-15) as outputs.
In the cases of Motorola non-multiplexed and multiplexed bus operations, this input is R/W. This input controls
the direction of the data bus lines (AD0-7, D8-15) during a microprocessor access. For Intel multiplexed bus
operation, this input is
WR.
This active LOW input is used with
RD
to control the data bus (AD0-7) lines as inputs.
Active LOW input used by a microprocessor to activate the microprocessor port of IDT72V70190.
This input is used if multiplexed bus operation is selected via the IM input pin. For Motorola non-multiplexed
bus operation, connect this pin to ground.
When IM is HIGH, the microprocessor port is in the multiplexed mode. When IM is LOW, the microprocessor
port is in non-multiplexed mode.
These pins are the eight least significant data bits of the microprocessor port. In multiplexed mode, these pins
are also the input address bits of the microprocessor port.
These pins are the eight most significant data bits of the microprocessor port.
This active LOW output signal indicates that a data bus transfer is complete. When the bus cycle ends, this pin
drives HIGH and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A
pull-up resistor is required to hold a HIGH level when the pin is in high-impedance.
This is a 4.096 Mb/s output containing 512 bits per frame respectively. The level of each bit is determined by
the CCO bit in the connection memory. See External Drive Control Section.
This is the output enable control for the TX0 to TX7 serial outputs. When ODE input is LOW and the OSB
bit of the IMS register is LOW, TX0-7 are in a high-impedance state. If this input is HIGH, the TX0-7
output drivers are enabled. However, each channel may still be put into a high-impedance state by using the
per channel control bit in the connection memory.
O
I
I
I
I
I
A0-7
DS/RD
Address 0-7
Data Strobe/Read
I
I
R/W /
WR
Read/Write / Write
I
CS
AS/ALE
IM
AD0-7
D8-15
DTA
Chip Select
Address Strobe or
Latch Enable
CPU Interface Mode
I
I
I
Address/Data Bus 0 to 7 I/O
Data Bus 8-15
Data Transfer
Acknowledgment
Control Output
Output Drive Enable
I/O
O
CCO
ODE
O
I
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IDT72V70190 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 256 x 256
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL DESCRIPTION
The IDT72V70190 is capable of switching 256 x 256, 64 Kbit/s PCM or N
x 64 Kbit/s channel data. The device maintains frame integrity in data applications
and minimum throughput delay for voice applications on a per channel basis.
The serial input streams of the IDT72V70190 can have a bit rate of
2.048 Mb/s and are arranged in 125µs wide frames, which contain 32 channels
respectively. The data rates on input and output streams are identical.
In Processor Mode, the microprocessor can access input and output time-
slots on a per channel basis allowing for transfer of control and status information.
The IDT72V70190 automatically identifies the polarity of the frame synchroni-
zation input signal and configures the serial streams to either ST-BUS
®
or GCI
formats.
With the variety of different microprocessor interfaces, IDT72V70190 has
provided an Input Mode pin (IM) to help integrate the device into different
microprocessor based environments: Non-multiplexed or Multiplexed. These
interfaces provide compatibility with multiplexed and Motorola non-multiplexed
buses. The device can also resolve different control signals eliminating the use
of glue logic necessary to convert the signals (R/W/WR, DS/RD, AS/ALE).
The frame offset calibration function allows users to measure the frame offset
delay using a frame evaluation pin (FE). The input offset delay can be
programmed for individual streams using internal frame input offset registers, see
Table 8.
The internal loopback allows the TX output data to be looped around to the
RX inputs for diagnostic purposes.
A functional Block Diagram of the IDT72V70190 is shown in Figure 1.
DATA AND CONNECTION MEMORY
The received serial data is converted to parallel format by internal serial-
to-parallel converters and stored sequentially in the data memory. The 8KHz
input frame pulse (F0i) is used to generate channel and frame boundaries of
the input serial data. Depending on the interface mode select (IMS) register,
the usable data memory may be as large as 256 bytes.
Data to be output on the serial streams (TX0-7) may come from either the
data memory or connection memory. For data output from data memory
(connection mode), addresses in the connection memory are used. For data
to be output from connection memory, the connection memory control bits must
set the particular TX output in Processor Mode. One time-slot before the data
is to be output, data from either connection memory or data memory is read
internally. This allows enough time for memory access and parallel-to-serial
conversion.
CONNECTION AND PROCESSOR MODES
In the Connection Mode, the addresses of the input source data for all output
channels are stored in the connection memory. The connection memory is
mapped in such a way that each location corresponds to an output channel on
the output streams. For details on the use of the source address data (CAB and
SAB bits), see Table 10. Once the source address bits are programmed by the
microprocessor, the contents of the data memory at the selected address are
transferred to the parallel-to-serial converters and then onto a TX output stream.
By having the each location in the connection memory specify an input
channel, multiple outputs can specify the same input address. This can be a
powerful tool used for broadcasting data.
In Processor Mode, the microprocessor writes data to the connection
memory. Each location in the connection memory corresponds to a particular
output stream and channel number and is transferred directly to the parallel-to-
serial converter one time-slot before it is to be output. This data will be output
4
on the TX streams in every frame until the data is changed by the microprocessor.
As the IDT72V70190 can be used in a wide variety of applications, the device
also has memory locations to control the outputs based on operating mode.
Specifically, the IDT72V70190 provides five per-channel control bits for the
following functions: processor or connection mode, constant or variable delay,
enables/three-state the TX output drivers and enables/disable the loopback
function. In addition, one of these bits allows the user to control the CCO output.
If an output channel is set to a high-impedance state through the connection
memory, the TX output will be in a high-impedance state for the duration of that
channel. In addition to the per-channel control, all channels on the ST-BUS
®
outputs can be placed in a high impedance state by either pulling the ODE input
pin low or programming the Output Stand-By (OSB) bit in the interface mode
selection register. This action overrides the per-channel programming in the
connection memory bits.
The connection memory data can be accessed via the microprocessor
interface. The addressing of the devices internal registers, data and connection
memories is performed through the address input pins and the Memory Select
(MS) bit of the control register. For details on device addressing, see Software
Control and Control Register bits description (Table 3 and 5).
SERIAL DATA INTERFACE TIMING
The master clock frequency must always be twice the data rate. For serial
data rates of 2.048 Mb/s, the master clock (CLK) must be at 4.096 MHz. The
input and output stream data rates will always be identical.
The input 8 KHz frame pulse can be in either ST-BUS
®
or GCI format. The
IDT72V70190 automatically detects the presence of an input frame pulse and
identifies it as either ST-BUS
®
or GCI. In ST-BUS
®
format, every second falling
edge of the master clock marks a bit boundary and the data is clocked in on the
rising edge of CLK, three quarters of the way into the bit cell, see Figure 7. In
GCI format, every second rising edge of the master clock marks the bit boundary
and data is clocked in on the falling edge of CLK at three quarters of the way
into the bit cell, see Figure 8.
INPUT FRAME OFFSET SELECTION
Input frame offset selection allows the channel alignment of individual input
streams to be offset with respect to the output stream channel alignment (i.e.
F0i).
Although all input data comes in at the same speed, delays can be caused by
variable path serial backplanes and variable path lengths which may be
implemented in large centralized and distributed switching systems. Because
data is often delayed, this feature is useful in compensating for the skew between
clocks.
Each input stream can have its own delay offset value by programming the
frame input offset registers (FOR). The maximum allowable skew is +4.5 master
clock (CLK) periods forward with resolution of ½ clock period. The output frame
offset cannot be offset or adjusted. See Figure 5, Table 8 and 9 for delay offset
programming.
SERIAL INPUT FRAME ALIGNMENT EVALUATION
The IDT72V70190 provides the frame evaluation (FE) input to determine
different data input delays with respect to the frame pulse
F0i.
A measurement cycle is started by setting the start frame evaluation (SFE)
bit low for at least one frame. When the SFE bit in the IMS register is changed
from low to high, the evaluation starts. Two frames later, the complete frame
evaluation (CFE) bit of the frame alignment register (FAR) changes from low
to high to signal that a valid offset measurement is ready to be read from bits 0
to 11 of the FAR register. The SFE bit must be set to zero before a new
IDT72V70190 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 256 x 256
COMMERCIAL TEMPERATURE RANGE
measurement cycle started.
In ST-BUS
®
mode, the falling edge of the frame measurement signal (FE)
is evaluated against the falling edge of the ST-BUS
®
frame pulse. In GCI mode,
the rising edge of FE is evaluated against the rising edge of the GCI frame pulse.
See Table 7 and Figure 4 for the description of the frame alignment register.
MEMORY BLOCK PROGRAMMING
The IDT72V70190 provides users with the capability of initializing the entire
connection memory block in two frames. To set bits 11 to 15 of every connection
memory location, first program the desired pattern in bits 5 to 9 of the IMS register.
The block programming mode is enabled by setting the memory block
program (MBP) bit of the control register high. When the block programming
enable (BPE) bit of the IMS register is set to high, the block programming data
will be loaded into the bits 11 to 15 of every connection memory location. The
other connection memory bits (bit 0 to bit 10) are loaded with zeros. When the
memory block programming is complete, the device resets the BPE bit to zero.
LOOPBACK CONTROL
The loopback control (LPBK) bit of each connection memory location allows
the TX output data to be looped backed internally to the RX input for diagnostic
purposes.
If the LPBK bit is high, the associated TX output channel data is internally
looped back to the RX input channel (i.e., data from TX n channel m routes to
the RX n channel m internally); if the LPBK bit is low, the loopback feature is
disabled. For proper per-channel loopback operation, the contents of frame
delay offset registers must be set to zero.
delay mode will be one frame. For example, when input time-slot 31 is switched
to output time-slot 0. The maximum delay of 94 time-slots of delay occurs when
time-slot 0 in a frame is switched to time-slot 31 in the frame. See Table 2.
MICROPROCESSOR INTERFACE
The IDT72V70190 provides a parallel microprocessor interface for multi-
plexed or non-multiplexed bus structures. This interface is compatible with
Motorola non-multiplexed and multiplexed buses.
If the IM pin is low a Motorola non-multiplexed bus should be connected to
the device. If the IM pin is high, the device monitors the AS/ALE and DS/RD to
determine what mode the IDT72V70190 should operate in.
If DS/RD is low at the rising edge of AS/ALE, then the mode 1 multiplexed
timing is selected. If DS/RD is high at the rising edge of AS/ALE, then the mode
2 multiplexed bus timing is selected.
For multiplexed operation, the required signals are the 8-bit data and
address (AD0-AD7), 8-bit Data (D8-D15), Address strobe/Address latch
enable (AS/ ALE), Data strobe/Read (DS/RD), Read/Write /Write (R/W /
WR),
Chip select (CS) and Data transfer acknowledge (DTA). See Figure 11 and
Figure 12 for multiplexed parallel microport timing.
For the Motorola non-multiplexed bus, the required signals are the 16-bit
data bus (AD0-AD7, D8-D15), 8-bit address bus (A0-A7) and 4 control lines
(CS, DS, R/W and
DTA).
See Figure 13 and 14 for Motorola non-multiplexed
microport timing.
The IDT72V70190 microport provides access to the internal registers,
connection and data memories. All locations provide read/write access except
for the data memory and the frame alignment register which are read only.
MEMORY MAPPING
The address bus on the microprocessor interface selects the internal
registers and memories of the IDT72V70190.
If the A7 address input is low, then A6 through A0 are used to address the
interface mode selection (IMS), control (CR), frame alignment (FAR) and frame
input offset (FOR) registers (Table 4). If the A7 is high, A6 and A5 are low, then
A4 through A0 are used to select 32 locations corresponding to data rate of the
ST-BUS
®
. The address input lines and the stream address bits (STA) of the
control register allow access to the entire data and connection memories. The
control and IMS registers together control all the major functions of the device,
see Figure 3.
As explained in the Serial Data Interface Timing and Switching Configura-
tions sections, after system power-up, the IMS register should be programmed
immediately to establish the desired switching configuration.
The data in the control register consists of the memory block programming
bit (MBP), the memory select bit (MS) and the stream address bits (STA). As
explained in the Memory Block Programming section, the MBP bit allows the
entire connection memory block to be programmed. The memory select bit is
used to designate the connection memory or the data Memory. The stream
address bits select internal memory subsections corresponding to input or output
serial streams.
The data in the IMS register consists of block programming bits (BPD0-
BPD4), block programming enable bit (BPE), output stand by bit (OSB) and start
frame evaluation bit (SFE). The block programming and the block programming
enable bits allows users to program the entire connection memory (see Memory
Block Programming section). If the ODE pin is low, the OSB bit enables (if high)
or disables (if low) all ST-BUS
®
output drivers. If the ODE pin is high, the contents
of the OSB bit is ignored and all TX output drivers are enabled.
DELAY THROUGH THE IDT72V70190
The switching of information from the input serial streams to the output serial
streams results in a throughput delay. The device can be programmed to
perform time-slot interchange functions with different throughput delay capabili-
ties on the per-channel basis. For voice applications, variable throughput delay
is best as it ensures minimum delay between input and output data. In wideband
data applications, constant throughput delay is best as the frame integrity of the
information is maintained through the switch.
The delay through the device varies according to the type of throughput
delay selected in the
V/C
bit of the connection memory.
VARIABLE DELAY MODE (V/C BIT = 0)
In this mode, the delay is dependent only on the combination of source and
destination channels and is independent of input and output streams. The
minimum delay achievable in the IDT72V70190 is three time-slots. If the input
channel data is switched to the same output channel (channel n, frame p), it will
be output in the following frame (channel n, frame p+1). The same is true if input
channel n is switched to output channel n+1 or n+2. If the input channel n is
switched to output channel n+3, n+4,..., the new output data will appear in the
same frame. Table 1 shows the possible delays for the IDT72V70190 in the
variable delay mode.
CONSTANT DELAY MODE (V/C BIT = 1)
In this mode, frame integrity is maintained in all switching configurations by
making use of a multiple data memory buffer. Input channel data is written into
the data memory buffers during frame n will be read out during frame n+2. In
the IDT72V70190, the minimum throughput delay achievable in the constant
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