PRELIMINARY
CM9107
Triple-Output LDO for WLAN
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
3.0V to 3.6V input voltage range
Preset output voltage with excellent line and load
regulation
LDO1 = 1.80V/500mA, ±1.5% max load regulation
LDO2 = 2.84V/300mA, ±1% max load regulation
LDO3 = 2.84V/200mA, ±1% max load regulation
Low output noise (<30µVrms for LDO3)
Low dropout voltage; 135mV (typ.) for LDO2 at
300mA, and 110mV (typ.) for LDO3 at 200mA.
Low quiescent current, < 600µA typical
Integrated microprocessor RESET circuit with
adjustable RESET delay (2.5ms per
-
nF of C
T
)
Logic controlled shutdown
Power good signal
Built-in power up and power down sequence con
trol between LDO1 and LDO2
Over-temperature and over-current protection
TQFN-16, RoHS compliant lead-free package
Product Description
The CM9107 is a triple-output, low noise, low dropout
(LDO) linear regulator with an integrated microproces
sor reset circuit. It is designed for use with wireless
local-area network chipsets. It has an input voltage
range of 3.0V to 3.6V, and supplies a 500mA, 1.80V
preset output (LDO1); a 300mA, 2.84V output (LDO2),
and a 200mA, low noise output of 2.84V (LDO3). The
CM9107 has excellent line and load regulation over the
operating temperature range.
The CM9107 LDOs features low dropout voltage by
using efficient P-channel MOSFETs for each output. It
also features a power good signal (active high) when
all three LDOs are in regulation. It provides two shut
down control pins, LDO1 and LDO2 power sequencing,
plus short-circuit and over-temperature shutdown pro
tection.
The CM9107 also provides a microprocessor RESET
circuit with RST and RST outputs. The RESET signal
is asserted when the V
IN
supply voltage drops below
2.63V, remaining asserted for the adjustable RESET
delay period, controlled by an external capacitor on the
CT pin.
The CM9107 is packaged in a 16-pin TQFN (4mm x
4mm) package. It can operate over the industrial tem
perature range of –40°C to 85°C.
Applications
•
•
•
Wireless LAN 802.11 chipset power supply
Wireless LAN cards
Wireless instrumentation
Typical Application
3.0V to 3.6V
10uF
C
IN
16
RST
15
PGOOD
VIN3
14
VIN
13
1 RST
2
0.01uF
C
T
CT
12
VO1
11
C
o1
1.8V, 500mA
Baseband
3.3uF
2.84V, 300mA
C
o2
3.3uF
Processor/
MAC
CM9107
GND3
CB1
10
VO2
CC2
9
C
b
0.033uF
Analog
Circuitry
3 SHDN
4 SHDN3
CC3
VO3
5
6
7
8
2.84V, 200mA
VCO
GND
C
o3
3.3uF
©
2006 California Micro Devices Corp. All rights reserved.
07/11/06
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
l
Tel: 408.263.3214
l
Fax: 408.263.7846
l
www.cmd.com
1
PRELIMINARY
CM9107
Package Pinout
PACKAGE / PINOUT DIAGRAM
TOP VIEW
(Pins Down View)
Pin 1
Marking
PGOOD
VIN3
RST
VIN
BOTTOM VIEW
(Pins Up View)
13
14
15
16
15
14
13
RST
CT
SHDN
SHDN3
1
12 VO1
12
11
10
9
16
1
CM910
700QE
2
3
4
11 CB1
10 VO2
9 CC2
GND
PAD
2
3
4
8
7
6
VO3 5
CC3 6
GND3 7
CM9107-00QE
16-Lead TQFN Package (4mmx4mm)
Note: This drawing is not to scale.
LEAD(s)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
NAME
DESCRIPTION
Reset bar pin. This is the inverse output of the RST signal pin (pin 16).
CT pin for setting the delay time for RST assert (2.5ms per nF).
Shutdown control input pin for LDO1 and LDO2. Active low, LDO1 and LDO2 will be off when
the pin is pulled low. Connect to V
IN
when unused.
Shutdown control input pin for LDO3. Active low. Connect to V
IN
when unused.
LDO3 output pin (2.84V). Connect a low-ESR bypass capacitor of 2.2µF, minimum.
This pin is used for testing. In the application it could be either floating or tied to ground
Ground pin for LDO3
Ground pin for LDO1, LDO2 and control circuit
This pin is used for testing. In the application it could be either floating or tied to ground
LDO2 output pin (2.84V). Connect a low-ESR bypass capacitor of 2.2µF, minimum.
Bypass capacitor pin for internal bandgap reference (typically 0.033µF low-ESR type).
LDO1 output pin (1.80V). Connect a low-ESR bypass capacitor of 2.2µF, minimum.
Power input pin for LDO2 and LDO3. Connect to a low-ESR bypass capacitor of 2.2µF,
minimum.
Power input pin for LDO3. Connect to Pin 13, on the PC board, very near the device.
Power good output pin with internal pull-up resistor to VIN, goes high when all 3 LDOs are in
regulation.
RST
CT
SHDN
SHDN3
VO3
CC3
GND3
GND
CC2
VO2
CB1
VO1
VIN
VIN3
PGOOD
©
2006 California Micro Devices Corp. All rights reserved.
2
GND 8
PIN DESCRIPTIONS
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
l
Tel: 408.263.3214
l
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Fax: 408.263.7846
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07/11/06
PRELIMINARY
CM9107
Pin Descriptions (cont’d)
PIN DESCRIPTIONS
16
RST
Reset output pin. When V
IN
falls below the RESET threshold, this RST pin is asserted (active
high). When V
IN
rises above the RESET threshold, RST goes low after a delay of 2.5ms per
nF of CT capacitance. Refer to RESET section in the Application Information.
Ordering Information
PART NUMBERING INFORMATION
Lead Free Finish
Pins
16
Package
TQFN
Ordering Part Number
1
CM9107-00QE
Part Marking
CM9107 00QE
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER
ESD Protection (HBM)
V
IN
, V
IN3
, GND3 to GND
Pin Voltages
V
O1
, V
O2
, V
O3
to GND
C
B1
to GND to GND
SHDN, SHDN3 to GND
CT, RST, RST, PGOOD to GND
Storage Temperature Range
Operating Temperature Range (Ambient)
Lead Temperature (Soldering, 10sec)
RATING
±2
[GND - 0.3] to +6.0
[GND - 0.3] to +6.0
[GND - 0.3] to +6.0
[GND - 0.3] to +5.0
[GND - 0.3] to +5.0
-65 to +150
-40 to +85
300
UNITS
kV
V
V
V
V
V
°C
°C
°C
ELECTRICAL OPERATING CHARACTERISTICS
(SEE NOTE 1)
SYMBOL
V
IN
I
Q
V
SHDN
V
IL
V
IH
T
START
PARAMETER
Input Supply Voltage
Quiescent Current
Shutdown Supply Current
Shutdown (active low) Input
Low Threshold
Shutdown Input High Threshold
Start-up Time (from SHDN
going high to V
OUT
in
regulation) (Note 3)
All outputs are no load
SHDN = SHDN3 = 0
CONDITIONS
MIN
3.0
TYP
3.3
600
5.0
MAX
3.6
750
10
0.4
2.0
V
OUT
= 95% of final value
120
UNITS
V
µA
µA
V
V
µs
©
2006 California Micro Devices Corp. All rights reserved.
07/11/06
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
l
Tel: 408.263.3214
l
Fax: 408.263.7846
l
www.cmd.com
3
PRELIMINARY
CM9107
Specifications (cont’d)
ELECTRICAL OPERATING CHARACTERISTICS
(SEE NOTE 1)
SYMBOL
T
PGOOD
O
PGOOD
T
OVER
T
HYS
UVLO
LDO1
V
OUT
V
OUT acc
I
LIM
V
R LIN
V
R LOAD
V
OUT N
LDO2
V
OUT
V
OUT acc
I
LIM
V
R LIN
V
R LOAD
V
DROP
V
OUT N
LDO3
V
OUT
V
OUT acc
I
LIM
V
R LIN
V
R LOAD
V
DROP
V
OUT N
RESET
T
RESET
T
HYS RESET
V
DROP RESETD
T
RST
Output Voltage
Output Voltage Accuracy
Over-current Limit (Note 2)
Line Regulation
Load Regulation (Note 5)
Dropout Voltage (Note 4)
Output Noise
V
IN3
= 3.0V to 3.6V, I
OUT
= 10mA
I
OUT
= 10mA to 200mA
I
OUT
= 200mA
10Hz < f < 100kHz, I
OUT
= 10mA
Co3 = 2.2µF
Co3 = 10µF
I
OUT
= 10mA
-1.5
250
-0.15
0.2
110
30
20
450
0.15
1.0
200
2.84
+1.5
V
%
mA
%/V
%
mV
µVrms
µVrms
Output Voltage
Output Voltage Accuracy
Over-current Limit (Note 2)
Line Regulation
Load Regulation (Note 5)
Dropout Voltage (Note 4)
Output Noise
V
IN
= 3.0V to 3.6V, I
OUT
= 10mA
I
OUT
= 10mA to 300mA
I
OUT
= 30 mA
10Hz < f < 100kHz, I
OUT
= 10mA
Co2 = 2.2µF
Co2 = 10µF
I
OUT
= 10mA
-1.5
330
-0.15
0.2
135
70
60
550
0.15
1.0
220
2.84
+1.5
V
%
mA
%/V
%
mV
µVrms
µVrms
PARAMETER
PGOOD Threshold
PGOOD Output Level
OTP Threshold
OTP Hysteresis
Undervoltage Lockout (Note 2)
Output Voltage
Output Voltage Accuracy
Over-current Limit (Note 2)
Line Regulation
Load Regulation (Note 5)
Output Noise
V
IN
= 3.0V to 3.6V, I
OUT
= 10mA
I
OUT
=10mA to 500mA
10Hz < f < 100kHz, Co1 = 3.3µF,
I
OUT
= 50mA
I
OUT
= 10mA
-1.5
550
-0.15
-1.5
100
750
0.15
1.5
All outputs are no load.
2.20
CONDITIONS
All output currents = 50% rating
I
SINK
= 2mA
150
20
2.45
1.80
+1.5
2.65
MIN
-5
TYP
MAX
+5
0.25
UNITS
%
V
ºC
ºC
V
V
%
mA
%/V
%
µVrms
RESET Threshold (Vth) (Note
2)
RESET Threshold Hysteresis
V
IN
Dropout Reset Delay
RST / RST Timeout Period
(Note 2)
V
CC
= Vth to Vth –100mV
CT = 10nF
2.56
2.63
10
20
2.69
V
mV
µs
ms
25
©
2006 California Micro Devices Corp. All rights reserved.
4
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
l
Tel: 408.263.3214
l
Fax: 408.263.7846
l
www.cmd.com
07/11/06
PRELIMINARY
CM9107
Specifications (cont’d)
ELECTRICAL OPERATING CHARACTERISTICS
(SEE NOTE 1)
SYMBOL
V
RST_L
V
RST_H
I
Q RST
PARAMETER
RST / RST Output Low Signal
RST / RST Output High Signal
RESET Block Quiescent
Current
.8 x
V
IN
4
CONDITIONS
MIN
TYP
MAX
0.4
UNITS
V
V
µA
Note 1: V
IN
= V
IN3
= 3.3V. C
IN
= 10µF, C
O
1 = C
O
2 = C
O
3 = 3.3µF, C
B
= 33nF. T
A
= 25°C unless otherwise specified.
Note 2: Parameter is guaranteed by design, not production tested.
Note 3: The start-up time is defined as from SHDN pin goes high until Vo1 reaches regulation; or from SHDN3 goes high until VO3
reaches regulation.
Note 4: The dropout voltage is defined as Vind– Vod, where Vod is 50mV below V
OUT
value measured at V
IN
= 3.3V.
Note 5: Regulation is measured at constant junction temperature using low duty cycle pulse testing.
Functional Block Diagram
CC2
3.3V VIN
C
IN
10uF
CC3
CB1
C
b
UVLO &
Bandgap
LDO1
0.033uF
1.8V
500mA
C
O1
3.3uF
PGOOD
Pgood
Logic
Window
Comparator
VO1
GND
LDO2
SHDN
SHDN3
Control
Logic
Enables
Window
Comparator
2.84V
VO2
300mA
C
O2
3.3uF
VIN
RST
RST
CT
C
T
.01uF
OTP
150
o
C
LDO3
Reset
Circuit
VIN3
2.84V
200mA
C
O3
Window
Comparator
VO3
CM9107
GND3
3.3uF
©
2006 California Micro Devices Corp. All rights reserved.
07/11/06
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
l
Tel: 408.263.3214
l
Fax: 408.263.7846
l
www.cmd.com
5
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