CA82C54
PROGRAMMABLE INTERVAL TIMER
• A high performance device featuring pin and
functional compatibility with the industry
standard 8254
• Supports 8086/88 and 80186/188 micro-
processors
• High Speed: zero wait state 10 MHz and 8 MHz
versions available
• Low power CMOS implementation
• TTL input/output compatibility
• Compatible with 8080/85, 8086/88, 80286/386 and
68000
µP
families
• Fully static operation
• Three independent 16 bit counters
• Six programmable counter modes
• Status read-back command
• Binary or BCD counting
The CA82C54 is a counter/timer device that includes
complete pin and functional compatibility with the industry
standard 8254. Designed for fast 10 MHz operation, it has
three independently programmable 16 bit counters and six
programmable counter modes. Counting can be performed in
both binary and BCD formats.
The CA82C54 offers a very flexible, hardware solution to
the generation of accurate time delays in microprocessor
systems. A general purpose, multi-timing element, it can be
used to implement event counters, elapsed time indicators,
waveform generators plus a host of other functions.
The low power consumption of the CA82C54 makes it
ideally suited to portable systems or those with low power
standby modes.
2
2.4
CA82C54
D5
D6
D7
NC
VDD
WR
RD
D4
D3
D2
D1
D0
CLK0
NC
5
6
7
8
9
10
11
12
13
14
15
16
17
18
25
24
23
NC
CS
A1
A0
CLK2
OUT2
GATE2
D7
D6
D5
D4
D3
D2
D1
D0
CLK 0
OUT 0
GATE 0
VSS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
VDD
WR
RD
CS
A1
A0
CLK 2
OUT 2
GATE 2
CLK 1
GATE 1
OUT 1
4
3
2
1
28
27
26
CA82C54
CA82C54
22
21
20
19
20
19
18
17
16
15
14
13
GATE0
VSS
NC
OUT1
GATE1
OUT0
Figure 2-1: PLCC Pin Configurations
CLK1
Figure 2-2: PDIP Pin Configurations
Tundra Semiconductor Corporation
2-69
CA82C54
Tundra Semiconductor Corporation
FUNCTIONAL DESCRIPTION
The CA82C54 is a versatile programmable interval
timer/counter designed for use in high speed 8, 16 and 32-bit
microprocessor systems. It provides a means of generating
accurate time delays in hardware that is fully software
configurable. It can be treated as an array of I/O ports, with
minimal software overhead.
The internal structure of the CA82C54 is illustrated in the
block diagram of Figure 2-3. Major functional blocks
include a data bus buffer, read/write logic, control word
register, and three programmable counters.
Data Bus Buffer Block
The 8-bit, 3-state data bus buffer provides controllable, bi-
directional interface between the CA82C54 and the
microprocessor system bus.
Read/Write Logic Block
The read/write logic block generates internal control signals
for the different functional blocks using address and control
information obtained from the system. The active LOW
signals;
CS
,
RD
and
WR
are used to select the CA82C54 for
operation, read a counter, and write to a counter (or the
control word register) respectively.
CS
must be LOW for
RD
or
WR
to be recognized. Note that
RD
and
WR
must NOT be
active at the same time.
The inputs A
0
and A
1
are used to select the control word
register, or one of the three counters that is to be written to or
read from (see Table 2-1). A
0
and A
1
connect directly to the
corresponding signals of the microprocessor address bus,
while
CS
is derived from the address bus using either a linear
select method, or an address decoder device.
Control Word Register
The control word register is a write only register that is
selected by the read/write logic block when A
0
and A
1
= 1.
When
CS
and
WR
are LOW, data is written into the CA82C54
control word register from the CPU via the data bus buffer.
Control word data is interpreted as a number of different
commands which are used to program the various device
functions. For example, status information is available with
the Read-Back Command. These are discussed further in the
section on programming.
Counter Blocks
The CA82C54 contains three identical, independent counter
blocks. Each counter provides the same functions, but can be
programmed to operate in different modes relative to each
other. A typical CA82C54 counter is illustrated in Figure 2-
4, and contains the following functional elements: control
logic, counter, output latches, count registers and status
register.
The Control Logic provides the interface between the
counter proper, the program instructions contained in the
control word register and the external signals CLK n, GATE
n and OUT n. It also keeps the status register information
current, controls the access of OL and CR to the internal data
bus, and the loading of CE from the CR registers.
The Counter proper (shown in the Figure 2-4 as CE, for
counting element) is a 16-bit presettable synchronous down
counter.
The Output Latches (shown as OL
M
and OL
L
) provide a
mechanism whereby the CPU can read the current contents
of the CE. These two 8-bit latches (M for most significant
byte and L for least significant byte) together form a 16-bit
latch capable of holding the complete contents of the CE.
Note that this arrangement is also convenient for
communicating 16-bit values over the 8-bit internal data bus.
During normal operation, the contents of OL track with the
contents of CE. When a Counter Latch Command is issued
by the CPU to a particular counter, its OL latches the current
value of CE so that it can be read by the CPU (the CE cannot
be read directly). OL then returns to tracking with CE. Note
that only one latch (OL
M
followed by OL
L
) at a time is
enabled by the counter's control logic.
The Count Registers (shown as CR
M
and CR
L
) behave as
input latches to the CE, and provide a mechanism whereby
the initial count value can be downloaded from the CPU to
the CE. Similar in operation to OL, CR is controlled by the
counter control logic. When a two byte initial count is to be
downloaded, it is transferred one byte at a time across the
internal CA82C54 data bus to the appropriate register (CR
M
if the most significant byte, CR
L
otherwise). CE is loaded by
transferring both bytes simultaneously from CR. Note that
CR is the interface between CE and the data bus, since CE
cannot be accessed directly.
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Tundra Semiconductor Corporation
Tundra Semiconductor Corporation
CA82C54
Both CR
M
and CR
L
are cleared automatically when the counter is programmed and a new initial count is to be written. Thus,
regardless of the counter's previous programming, both CR bytes will be initialized to a known zero state. This is important in
the case where one byte counts are programmed (either most significant or least significant byte), so that the unused byte is
always zero, and won't corrupt the initial count value loaded into CE.
The Status Register and Latch is used to hold the current contents of the control word register and the status of the output and
null count flag (see section on Programming). The contents of the status register must be latched to become available to the
data bus, where they can be read by the CPU.
Note that the Control Word Register is also shown in the Counter block diagram. While not a part of the counter proper, its
contents determine the functional operation of the counter, including mode selections programmed.
8-BIT INTERNAL BUS
CONTROL
WORD
REGISTER
STATUS
LATCH
CR
M
STATUS
REGISTER
CR
L
CONTROL
LOGIC
CE
(16-BIT DOWN COUNTER)
OL
M
GATEn
CLKn
OUTn
OL
L
Figure 2-4: Block Diagram of a Counter
Tundra Semiconductor Corporation
2-73
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